MT18HTF12872PDY-40ED2

PDF: 09005aef80e935cd/Source: 09005aef80e934a6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72D.fm - Rev. E 2/07 EN
4 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Symbol Type Description
ODT0, ODT1 Input
(SSTL_18)
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
CK0, CK0# Input
(SSTL_18)
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0, CKE1 Input
(SSTL_18)
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
S0#, S1# Input
(SSTL_18)
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
RAS#, CAS#,
WE#
Input
(SSTL_18)
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
BA0, BA1
(512MB, 1GB)
BA0, BA1, BA2
(2GB)
Input
(SSTL_18)
Bank address inputs: BA0–BA1/BA2 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
A0–A12
(512MB)
A0–A13
(1GB, 2GB)
Input
(SSTL_18)
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
P
AR_IN Input
(SSTL_18)
Parity bit for the address and control bus.
SCL Input
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
SA0–SA2 Input
Presence-detect address inputs: These pins are used to configure the presence-detect
device.
RESET# Input
(LVCMOS)
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
used during power-up to ensure that CKE is LOW and DQs are High-Z.
DQS0–DQS8,
DQS0#–DQS17#
I/O (SSTL_18)
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
DM0–DM8
(DQS9–DQS17)
I/O (SSTL_18)
Data input mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. If RDQS is disabled, DQS0–DQS17 become DM0–DM8 and
DQS9#–DQS17# are not used.
DQ0–DQ63 I/O (SSTL_18)
Data input/output: Bidirectional data bus.
CB0–CB7 I/O (SSTL_18)
Check bits.
SDA I/O
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
E
RR_OUT Output
(open drain)
Parity error found on the address and control bus.
V
DD/VDDQ Supply
Power supply: 1.8V ±0.1V.
V
REF Supply
SSTL_18 reference voltage.
Vss Supply
Ground.
V
DDSPD Supply
Serial EEPROM positive power supply: +1.7V to +3.6V.
NC
No connect: These pins should be left unconnected.
RFU
Reserved for future use.
PDF: 09005aef80e935cd/Source: 09005aef80e934a6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72D.fm - Rev. E 2/07 EN
5 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
R
E
G
I
S
T
E
R
S
PAR_IN
S0#
S1#
BA0–BA1/BA2
A0–A12/A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
ERR_OUT
RS0#: U1–U5, U9–U12
RS1#: U13–U16, U18–U22
RBA0–RBA1/RBA2: DDR2 SDRAM
RA0–RA12/RA13: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: U1–U5, U9–U12
RCKE1: U13–U16, U18–U22
RODT0: U1–U5, U9–U12
RODT1: U13–U16, U18–U22
U6, U17
VREF
VSS
DDR2 SDRAM
DDR2 SDRAM
VDD\VDDQ
VDDSPD
SPD EEPROM
DDR2 SDRAM
A0
SPD EEPROM
A1
A2
SA0 SA1 SA2
SDASCL
WP
PLL
CK0
CK0#
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
Register x 2
RESET#
U8
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U22
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U16
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U21
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U15
DQS1
DQS1#
DM1/DQS10
NC/DQS10#
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U20
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U14
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
DQS6
DQS6#
DM6/DQS15
NC/DQS15#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U13
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
DQS7
DQS7#
DM7/DQS16
NC/DQS16#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U18
DQS8
DQS8#
DM8/DQS17
NC/DQS17#
RS1#
RS0#
VSS
PDF: 09005aef80e935cd/Source: 09005aef80e934a6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72D.fm - Rev. E 2/07 EN
6 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
General Description
General Description
The MT18HTF6472(P), MT18HTF12872(P), and MT18HTF25672(P) DDR2 SDRAM
modules are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB
memory modules organized in a x72 configuration. These DDR2 SDRAM modules use
internally configured 4-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
2
C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
SS on the
module, permanently disabling hardware write protect.

MT18HTF12872PDY-40ED2

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 1GB 240RDIMM
Lifecycle:
New from this manufacturer.
Delivery:
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