XC18V00 Series In-System Programmable Configuration PROMs
12 www.xilinx.com DS026 (v4.1) December 15, 2003
1-800-255-7778 Product Specification
R
Reset Activation
On power up, OE/RESET is held low until the XC18V00 is
active (1 ms). OE/RESET
is connected to an external 4.7kΩ
resistor to pull OE/RESET
HIGH releasing the FPGA INIT
and allowing configuration to begin. If the power drops
below 2.0V, the PROM resets. OE/RESET
polarity is not
programmable. See Figure 8 for power-up requirements.
Standby Mode
The PROM enters a low-power standby mode whenever
CE
is asserted High. The address is reset. The output
remains in a high-impedance state regardless of the state of
the OE input. JTAG pins TMS, TDI and TDO can be in a
high-impedance state or High. See Table 7.
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and also connected to the PROM
CE
pin to enable low-power standby mode, then an external
buffer should be used to drive the LED circuit to ensure valid
transitions on the PROMs CE
pin. If low-power standby
mode is not required for the PROM, then the CE
pin should
be connected to ground.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V
CCINT
power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
CCINT
), and the output power sup-
ply (V
CCO
) can have power applied in any order. This
makes the PROM devices immune to power supply
sequencing issues.
Customer Control Bits
The XC18V00 PROMs have various control bits accessible
by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx iMPACT soft-
ware. The iMPACT software can set these bits to enable the
optional JTAG read security, parallel configuration mode, or
CF-->D4 pin function. See Table 7.
Figure 8: V
CCINT
Power-Up Requirements
Time (ms)
Volts
3.6V
3.0V
0V
Recommended Operating Range
Recommended
V
CCINT
Rise
Time
1ms 50ms0ms
ds026_10_061103
Table 7: Truth Table for PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET CE DATA CEO I
CC
High Low If address < TC
(1)
: increment
If address > TC
(1)
: don’t change
Active
High-Z
High
Low
Active
Reduced
Low Low Held reset High-Z High Active
High High Held reset High-Z High Standby
Low High Held reset High-Z High Standby
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
