DS1087L
3.3V Spread-Spectrum EconOscillator
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Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of
the clock signal. The data on the line must be
changed during the LOW period of the clock sig-
nal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between START
and STOP conditions is not limited, and is deter-
mined by the master device. The information is
transferred byte-wise and each receiver acknowl-
edges with a ninth bit.
Within the bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz
clock rate) are defined. The DS1087L works in
both modes.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowl-
edge after the byte has been received. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during
the HIGH period of the acknowledge-related clock
pulse. Of course, setup and hold times must be
taken into account. When the DS1087L EEPROM
is being written to, it is not able to perform addi-
tional responses. In this case, the slave DS1087L
sends a not acknowledge to any data transfer
request made by the master. It resumes normal
operation when the EEPROM operation is com-
plete.
A master must signal an end of data to the slave
by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
Figures 3, 4, 5, and 6 detail how data transfer is
accomplished on the 2-wire bus. Depending upon
the state of the R/W bit, two types of data transfer
are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a not acknowledge is
returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus is not released.
The DS1087L can operate in the following two modes:
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted.
START and STOP conditions are recognized as
the beginning and end of a serial transfer.
Address recognition is performed by hardware
after reception of the slave address and direction
bit.
Slave transmitter mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates
that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1087L while the
serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and
end of a serial transfer.
Slave Address
Figure 4 shows the first byte sent to the device. It
includes the device identifier, device address, and the
R/W bit. The device address must match the address
set in the ADDR register (bits A0, A1, and A2).
Registers/Commands
See Table 1 for the complete list of registers/com-
mands and Figure 6 for an example of using them.
