DS1087LU-2CL+ Datasheet DS1087LU-466+, DS1087LU-2CL+, DS1087LU-210+ | P7-P9

DS1087L

3.3V Spread-Spectrum EconOscillator

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Pin Description

PIN NAME FUNCTION

1 OUT Oscillator Output

2 SPRD Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.

Power Supply

4 GND Ground

5OE

Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is

disabled but the internal master oscillator is still on.

6 PDN

Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master

oscillator is disabled (power-down mode).

7 SDA 2-Wire Serial Data. This pin is for serial data transfer to and from the device.

8 SCL 2-Wire Serial Clock. This pin is used to clock data into and out of the device.

Figure 1. Functional Diagram

SDA

SCL

2-WIRE

INTERFACE

EEPROM CONTROL

REGISTERS

PRESCALER

ADDR

SPRD

PDN

OUT

TRIANGLE WAVE

GENERATOR

FACTORY-PROGRAMMED

OSCILLATOR

PRESCALER

BY 1, 2, 4...256

GND

MASTER

OSCILLATOR

OUTPUT

DITHER SIGNAL

DITHER

CONTROL

DS1087L

3.3V Spread-Spectrum EconOscillator

8 _____________________________________________________________________

Detailed Description

A block diagram of the DS1087L is shown in Figure 1.

Output Frequency

The internal master oscillator can generate a square

wave with a frequency range of 33.3MHz to 66.6MHz.

The master oscillator frequency and output frequency

are factory programmed, although the user can use the

programmable divider to divide the master oscillator

frequency by 2

(where x equals 0 to 8).

Output Control and Power-Down

Two user control signals control the output. The output-

enable pin, OE, gates the clock output buffer and the

PDN pin disables the master oscillator and turns off the

output for power-sensitive applications (note: the

power-down command must persist for at least two out-

put frequency cycles plus 10µs for deglitching purpos-

es). On power-up, the output is disabled until power is

stable and the master oscillator has generated 512

clock cycles.

Both controls feature a synchronous enable, which

ensures there are no output glitches when the output is

enabled. The synchronous enable also ensures a con-

stant time interval (for a given frequency setting) from

an enable signal to the first output transition.

Spread Spectrum

The DS1087L can reduce radiated emission peaks. The

output frequency can be dithered 2% or 4% below the

programmed frequency. Although the output frequency

changes when the dither is enabled, the duty cycle

does not change.

The dither is controlled by the J0 bit in the PRESCALER

spectral attenuation occurs when the prescaler is set to

1. The spectral attenuation is reduced by 2.7dB for

every factor of 2 that is used in the prescaler. This hap-

pens because the prescaler’s divider function tends to

average the dither in creating the lower frequency.

However, the most stringent spectral emission limits are

imposed on the higher frequencies where the prescaler

is set to a low divider ratio.

A triangle-wave generator injects an offset element into

the master oscillator to dither its output. The dither rate

(see Equation 1) is based on the master oscillator fre-

quency. Figure 2 shows a plot of the output frequency

versus dither rate.

where f

= master oscillator frequency

The DS1087L registers are used to change the dither

amount, output frequency, and slave address. A sum-

mary of the registers is shown in Table 1. Once pro-

grammed into EEPROM, the settings only need to be

reprogrammed if it is desired to reconfigure the device.

PRESCALER Register

Bit 5: Output Low or High-Z. The LO/HIZ bit

controls the output. During power-down,

while the output is deactivated, if the

LO/HIZ bit is set to 0, the output is high-Z.

If the LO/HIZ bit is set to 1, the output is

driven low.

Bit 4: Dither Control. The J0 bit controls the

dither applied to the output. When J0 is

high, 2% peak dither is selected. When

J0 is low, 4% peak dither is selected.

Dither Rate

4096

PRESCALER 02h X

LO/

HIZ

J0 P3 P2 P1 P0 110- - - - - b R/W

ADDR 0Dh X

WC A2 A1 A0 11110000b R/W

WRITE EE 3Fh No Data — —

Table 1. Register Summary

Figure 2. Output Frequency vs. Dither Rate

OUTPUT FREQUENCY

DITHER RATE

WHERE N = (2

)

= FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY

/4096f

/4096

/N) - 4%

(1)

= Don’t care; read as one.

DS1087L

3.3V Spread-Spectrum EconOscillator

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Bits 3 to 0: Prescaler Divider. The prescaler bits

(bits P3 to P0) divide the master oscillator

frequency by 2

where x can be from 0 to

8. Any prescaler bit value entered that is

greater than 8 decodes as 8.

ADDR Register

Bit 3: Write Control. The WC bit determines if

the EEPROM is to be written to after reg-

ister contents have been changed. If WC

= 0 (default), EEPROM is written automat-

ically after a write. If WC = 1, the EEP-

ROM is only written when the WRITE EE

command is issued. See the WRITE EE

Command section for more information.

Bits 2 to 0: Address. The A0, A1, A2 bits determine

the lower nibble of the 2-wire slave

address.

WRITE EE Command

The WRITE EE command is useful in closed-loop appli-

cations where the registers are frequently written. In

applications where the register contents are frequently

written, the WC bit should be set to 1 to prevent wear-

ing out the EEPROM. Regardless of the value of the WC

bit, the value of the ADDR register is always written

immediately to EEPROM. When the WRITE EE com-

mand has been received, the contents of the registers

are copied into the EEPROM, thus locking in the regis-

ter settings.

_______2-Wire Serial Port Operation

2-Wire Serial Data Bus

The DS1087L communicates through a 2-wire serial

interface. A device that sends data onto the bus is

defined as a transmitter, and a device receiving data

as a receiver. The device that controls the message is

called a "master." The devices that are controlled by the

master are "slaves." A master device that generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions must control the

bus. The DS1087L operates as a slave on the 2-wire

bus. Connections to the bus are made through the

open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (see

Figures 3 and 5):

• Data transfer can be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH are

interpreted as control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

HIGH.

Start data transfer: A change in the state of the

data line, from HIGH to LOW, while the clock is

HIGH, defines a START condition.

Stop data transfer: A change in the state of the

data line, from LOW to HIGH, while the clock line

is HIGH, defines the STOP condition.

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12 678 9 12 893–7

Figure 3. 2-Wire Data Transfer Protocol

P1-P3 P4-P6 P7-P9 P10-P12

DS1087LU-2CL+

Mfr. #:

Buy DS1087LU-2CL+

Manufacturer:

Maxim Integrated

Description:

Clock Generators & Support Products 3.3V Spread-Spectrum EconOscillator

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DS1087LU-2CL+

DS1087LU-2CL+

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