STM1001 Operation
Doc ID 10373 Rev 6 7/18
2 Operation
2.1 Reset output
The STM1001 microprocessor reset circuit asserts a reset signal to the MCU whenever V
CC
goes below the reset threshold (V
RST
). RST is guaranteed valid down to V
CC
=1 V (0° to
70 °C).
During power-up, once V
CC
exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, t
rec
. After this interval, RST returns high.
If V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period. Any time V
CC
goes below the reset threshold, the
internal timer clears. The reset timer starts when V
CC
returns above the reset threshold. The
active-low reset (RST
) is an open drain output.
2.2 Negative-going V
CC
transients
The STM1001 is relatively immune to negative-going V
CC
transients (glitches). Figure 10 on
page 10 shows typical transient duration versus reset comparator overdrive (for which the
STM1001 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to V
CC
, starting at 0.5 V above the actual reset threshold and ending below it
by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse
width a negative V
CC
transient can have without causing a reset pulse. As the magnitude of
the transient increases (further below the threshold), the maximum allowable pulse width
decreases. Any combination of duration and overdrive which lies under the curve will NOT
generate a reset signal. Typically, a V
CC
transient that goes 100 mV below the reset
threshold and lasts 20 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor
mounted as close as possible to the V
CC
pin provides additional transient immunity.
