TSM900N10CP ROG Datasheet TSM900N10CH X0G, TSM900N10CP ROG | P1-P3

TSM900N10

Taiwan Semiconductor

Document Number: DS_P0000173 1 Version: A15

N-Channel Power MOSFET

100V, 15A, 90mΩ

FEATURES

● 100% avalanche tested

● Low gate charge for fast switching

● Pb-free plating

● RoHS compliant

● Halogen-free mold compound

APPLICATION

● Networking

● Load Switching

● LED Lighting Control

● AC-DC Secondary Rectification

KEY PERFORMANCE PARAMETERS

PARAMETER

VALUE

UNIT

V

DS

100

V

R

DS(on)

(max)

V

GS

= 10V

90

mΩ

V

GS

= 4.5V

100

Q

g

9.3

nC

TO-251S

(IPAK SL)

TO-252

(DPAK)

Notes: Moisture sensitivity level: level 3. Per J-STD-020

ABSOLUTE MAXIMUM RATINGS (T

A

= 25°C unless otherwise noted)

PARAMETER

SYMBOL

LIMIT

UNIT

Drain-Source Voltage

V

DS

100

V

Gate-Source Voltage

V

GS

±20

V

Continuous Drain Current

(Note 1)

T

C

= 25°C

I

D

15

A

T

C

= 100°C

9.5

Pulsed Drain Current

(Note 2)

I

DM

60

A

Total Power Dissipation @ T

C

= 25°C

P

DTOT

50

W

Single Pulsed Avalanche Energy

(Note 3)

E

AS

18

mJ

Single Pulsed Avalanche Current

(Note 3)

I

AS

6

A

Operating Junction and Storage Temperature Range

T

J

, T

STG

- 55 to +150

°C

THERMAL PERFORMANCE

PARAMETER

SYMBOL

LIMIT

UNIT

Junction to Case Thermal Resistance

R

ӨJC

2.5

°C/W

Junction to Ambient Thermal Resistance

R

ӨJA

62

°C/W

Notes: R

ӨJA

is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined

at the solder mounting surface of the drain pins. R

ӨJA

is guaranteed by design while R

ӨCA

is determined by the user’s board

design. R

ӨJA

shown below for single device operation on FR-4 PCB in still air.

TSM900N10

Taiwan Semiconductor

Document Number: DS_P0000173 2 Version: A15

ELECTRICAL SPECIFICATIONS (T

A

= 25°C unless otherwise noted)

PARAMETER

CONDITIONS

SYMBOL

MIN

TYP

MAX

UNIT

Static

(Note 4)

Drain-Source Breakdown Voltage

V

GS

= 0V, I

D

= 250µA

BV

DSS

100

--

V

Gate Threshold Voltage

V

DS

= V

GS

, I

D

= 250µA

V

GS(TH)

1.2

1.6

2.5

V

Gate Body Leakage

V

GS

= ±20V, V

DS

= 0V

I

GSS

--

±100

nA

Zero Gate Voltage Drain Current

V

DS

= 100V, V

GS

= 0V

I

DSS

--

1

µA

Drain-Source On-State Resistance

V

GS

= 10V, I

D

= 5A

R

DS(on)

--

72

90

mΩ

V

GS

= 4.5V, I

D

= 3A

75

100

Dynamic

(Note 5)

Total Gate Charge

V

DS

= 48V, I

D

= 5A,

V

GS

= 10V

Q

g

--

9.3

--

nC

Gate-Source Charge

Q

gs

--

2.1

--

Gate-Drain Charge

Q

gd

--

1.8

--

Input Capacitance

V

DS

= 50V, V

GS

= 0V,

f = 1.0MHz

C

iss

--

1480

--

pF

Output Capacitance

C

oss

--

480

--

Reverse Transfer Capacitance

C

rss

--

35

--

Gate Resistance

F = 1MHz, open drain

R

g

--

1.3

--

Ω

Switching

(Note 6)

Turn-On Delay Time

V

DD

= 30V,

R

GEN

= 3.3Ω,

I

D

= 1A, V

GS

= 10V,

t

d(on)

--

2.9

--

ns

Turn-On Rise Time

t

r

--

9.5

--

Turn-Off Delay Time

t

d(off)

--

18.4

--

Turn-Off Fall Time

t

f

--

5.3

--

Source-Drain Diode

(Note 4)

Forward On Voltage

I

S

= 3.3A, V

GS

= 0V

V

SD

--

1

V

Continuous Drain-Source Diode

V

G

=V

D

=0V, Force Current

I

S

--

15

A

Pulse Drain-Source Diode

I

SM

--

60

A

Notes:

1. Current limited by package

2. Pulse width limited by the maximum junction temperature

3. L = 0.1mH, I

AS

= 6A, V

DD

= 50V, R

G

= 25Ω, Starting T

J

= 25

o

C

4. Pulse test: PW ≤ 300µs, duty cycle ≤ 2%

5. For DESIGN AID ONLY, not subject to production testing.

6. Switching time is essentially independent of operating temperature.

TSM900N10

Taiwan Semiconductor

Document Number: DS_P0000173 3 Version: A15

ORDERING INFORMATION (EXAMPLE)

PART NO.

PACKAGE

PACKING

TSM900N10CH X0G

TO-251S (IPAK SL)

75pcs / Tube

TSM900N10CP ROG

TO-252 (DPAK)

2,500pcs / 13” Reel

Note:

1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC

2. Halogen-free according to IEC 61249-2-21 definition

TSM900N10CP ROG

TSM900N10CP ROG

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