NCP5393
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TYPICAL CHARACTERISTICS
Figure 7. 12VMON Undervoltage Lockout
Threshold Voltage vs. Temperature
Figure 8. PWRGOOD Voltage vs. Temperature
T
J
, JUNCTION TEMPERATURE (°C) T
J
, JUNCTION TEMPERATURE (°C)
7550250
7.0
7.5
8.0
8.5
9.0
9.5
10
7550250
310
320
330
340
350
360
370
V
CC
UVLO THRESHOLD VOLTAGE (V)
PWRGOOD THRESHOLD VOLTAGE (mV)
V
CC
Increasing Voltage
V
CC
Decreasing Voltage
PWRGOOD Upper Voltage
PWRGOOD Lower Voltage
Functional Description
General
NCP5393 is an universal CPU Power Supply Controller
compatible with both Parallel (PVI) and Serial (SVI)
protocols for AMD Processors. The device provides
complete control logic and protections for a
high-performance step-down DC-DC voltage regulator,
optimized for advanced microprocessor power supply
supporting both PVI and SVI communication. It embeds two
independent controllers for CPU CORE and the integrated
NB, each one with its set of protections. The Controller
performs a single-phase control for the NB Section and a
programmable 2- to-4 phase control for the CORE Section
featuring Dual-Edge multiphase architecture.
NCP5393 also supports V_FIX mode for board debug: in
this particular configuration the SVI bus is used as a static
bus configuring 4 operative voltages for both the sections
and ignoring any serial-VID command. It can be used for
the board debug before plugging-in the CPU.
The NCP5393 incorporates differential voltage sensing,
differential phase current sensing, optional load-line
voltage positioning, and programmable VDD and VDDNB
offsets to provide accurately regulated power parallel- and
serial-VID AMD processors. Dual-edge multiphase
modulation provides the fastest initial response to dynamic
load events.
NCP5393 is able to detect which kind of CPU is connected
in order to configure itself to work as a Single-Plane PVI
controller or Dual-Plane SVI controller. The NCP5393
manages On the Fly VID transitions and maintains the slew
rates as defined when the transitions take place. NCP5393
is available in TQFN48 Package.
Remote Output Sensing Amplifier (RSA)
A true differential amplifier allows the NCP5393 to measure
Vcore voltage feedback with respect to the Vcore ground
reference point by connecting the Vcore reference point to VSP,
and the Vcore ground reference point to VSN. This
configuration keeps ground potential differences between the
local controller ground and the Vcore ground reference point
from affecting regulation of Vcore between Vcore and Vcore
ground reference points. The RSA also subtracts the DAC
(minus VID offset) voltage, thereby producing an unamplified
output error voltage at the DIFFOUT pin. This output also has
a 1.3 V bias voltage as the floating ground to allow both
positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided and system
trimmed. This DAC has 0.5% accuracy over the entire
operating temperature range of the part. The DAC can be
programmed to support both PVI and SVI VID code
specifications.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as the
controller of a voltage regulator, a capacitor from COMP to
VFB is required for stable unity gain test configurations.
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2-, 3-, or 4-phase
mode. In 2-phase mode, phases 1 and 3 should be used to
drive the external gate drivers, G2 and G4 must be grounded.
In 3-phase mode, gate output G4 must be grounded. In
4-phase mode all 4 gate outputs are used as shown in the
4-phase Applications Schematic. The Current Sense inputs
of unused channels should be connected to GND. Please
refer to table “PIN CONNECTIONS vs. PHASE COUNTS”
for details.
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Differential Current Sense Amplifiers and Summing
Amplifier
Four differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
sense amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase's current sense amplifier
must be shorted together and connected to the GND.
The current signals sensed from inductor DCR are fed into
a summing amplifier to have a summed-up output. The
outputs of current sense amplifiers control three functions.
First, the summing current signal of all phases will go
through DROOP amplifier and join the voltage feedback
loop for output voltage positioning. Second, the output
signal from DROOP amplifier also goes to ILIM amplifier
to monitor the output current limit. Finally, the individual
phase current contributes to the current balance of all phases
by offsetting their ramp signals of PWM comparators.
Oscillator and Triangle Wave Generator
The controller embeds a programmable precision
dual-Oscillator: one section is used for the CORE and it is
a multiphase programmable oscillator managing equal
phase-shift among all phases and the other section is used
for the NB section. The oscillator's frequency is
programmed by the resistance connected from the ROSC
pin to ground. The user will usually form this resistance
from two resistors in order to create a voltage divider that
uses the ROSC output voltage as the reference for creating
the current limit setpoint voltage. The oscillator frequency
range is 100_kHz per phase to 1.0_MHz per phase. The
oscillator generates up to 4 symmetrical triangle waveforms
with amplitude between 1.3_V and 2.3_V. The triangle
waves have a phase delay between them such that for 2-, 3-
and 4-phase operation the PWM outputs are separated by
180, 120, and 90 angular degrees, respectively.
When the NB phase is enabled, in order to ensure that the
VDDNB oscillator does not accidentally lock to the VDD
oscillator, the VDDNB oscillator will free-run at a
frequency which is nominally 1.25 ratio of f
VDD
.
CPU Support
NCP5393 is able to detect the CPU it is going to supply
and configure itself accordingly. At system Start-up, on the
rising-edge of the EN signal, the device monitors the status
of VID1 and switches in PVI mode (VID1 = 1) or SVI mode
(VID1 = 0). When in PVI mode, NCP5393 uses the
information available on the VID[0:5] bus to address the
CORE Section output voltage. NB Section is kept in HiZ
mode. When in SVI mode, NCP5393 discards the
information available on VID0, VID4 and VID5 and uses
VID2 and VID3 for SVC and SVD respectively.
PVI - Parallel Interface
PVI is a 6-bit-wide parallel interface used to address the
CORE Section reference. According to the selected code,
the device sets the CORE Section reference and regulates its
output voltage. NB Section is kept in HiZ; no activity is
performed on this section. furthermore, PWROK
information is ignored as well since the signal is propietary
of the SVI protocol. Start-up sequences before soft start and
after soft start are given in Figure 9. Voltage identifications
for the 6Bit AMD mode is given in Table 1.
Figure 9. Power Up Sequences Before and After Soft Start in PVI Mode
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Table 1. SIX-BIT PARALLEL VID CODES in PVI Modes
SVID[5:0] V
OUT
(V) SVID[5:0] V
OUT
(V) SVID[5:0] V
OUT
(V) SVID[5:0] V
OUT
(V)
00_0000 1.5500 01_0000 1.1500 10_0000 0.7625 11_0000 0.5625
00_0001 1.5250 01_0001 1.1250 10_0001 0.7500 11_0001 0.5500
00_0010 1.5000 01_0010 1.1000 10_0010 0.7375 11_0010 0.5375
00_0011 1.4750 01_0011 1.0750 10_0011 0.7250 11_0011 0.5250
00_0100 1.4500 01_0100 1.0500 10_0100 0.7125 11_0100 0.5125
00_0101 1.4250 01_0101 1.0250 10_0101 0.7000 11_0101 0.5000
00_0110 1.4000 01_0110 1.0000 10_0110 0.6875 11_0110 0.4875
10_0111 1.3750 01_0111 0.9750 10_0111 0.6750 11_0111 0.4750
00_1000 1.3500 01_1000 0.9500 10_1000 0.6625 11_1000 0.4625
00_1001 1.3250 01_1001 0.9250 10_1001 0.6500 11_1001 0.4500
00_1010 1.3000 01_1010 0.9000 10_1010 0.6325 11_1010 0.4375
00_1011 1.2750 01_1011 0.8750 10_1011 0.6250 11_1011 0.4250
00_1100 1.2500 01_1100 0.8500 10_1100 0.6125 11_1100 0.4125
00_1101 1.2250 10_1101 0.8250 10_1101 0.6000 11_1101 0.4000
00_1110 1.2000 01_1110 0.8000 10_1110 0.5875 11_1110 0.3875
00_1111 1.1750 01_1111 0.7750 10_1111 0.5750 11_1111 0.3750
SVI - Serial Interface
SVI is a two wire, Clock and Data, bus that connects a
single master (AMD processor) to one NCP5393. The
master initiates and terminates SVI transactions and drives
the clock, SVC, and the data SVD, during a transaction. The
slave receives the SVI transactions and acts accordingly.
SVI wire protocol is based on fast-mode I2C. The SVI
communications are given in Figure 10.
SVI interface also considers EN and PWROK signals for
start-up. The device returns a PWRGOOD signal if the
output voltages are in regulation. The VID codes for SVI are
given in Table 2.
The start-up sequences before and after soft start are
given in Figure 11.
Figure 10. SVI Communication - Send Byte

NCP5393MNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTLR 2/3/4PHASE CPU 48-QFN
Lifecycle:
New from this manufacturer.
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