NCP5393
http://onsemi.com
5
NCP5393 PIN DESCRIPTIONS
Pin No. Symbol Description
1 VCCA 5 V supply pin for the NCP5393. The V
CC
bypassing capacitance must be connected between this
pin and GND (preferably returned to the package flag).
2 GND Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad).
3 COMP Output of the voltage error amplifier for the V
DD
regulator.
4 FB Voltage error amplifier inverting input for the V
DD
regulator.
5 DROOP Voltage output signal proportional to total current drawn from the V
DD
regulator. Used when load line
operation (“droop”) is desired.
6 VS+ Non-inverting input to the differential remote sense amplifier for the V
DD
regulator.
7 VS- Inverting input to the differential remote sense amplifier for the V
DD
regulator.
8 OFFSET Input for offset voltage to be added to the V
DD
DAC's output voltage. Ground this pin for zero V
DD
offset.
9 DIFFOUT Output of the differential remote sense amplifier for the V
DD
regulator.
10 VFIX When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded
as a two-bit DAC code, which controls the V
DD
and VDDNB outputs.
11 12VMON UVLO monitor input for the 12 V power rail.
12 PSI_L Power Saving Control. Low = single phase operation, High = normal operation. This pin is not used in
SVI mode.
13 CS1 Non-inverting input to current sense amplifier #1 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
14 CS1N Inverting input to current sense amplifier #1 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
15 CS2 Non-inverting input to current sense amplifier #2 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
16 CS2N Inverting input to current sense amplifier #2 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
17 CS3 Non-inverting input to current sense amplifier #3 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
18 CS3N Inverting input to current sense amplifier #3 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
19 CS4 Non-inverting input to current sense amplifier #4 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
20 CS4N Inverting input to current sense amplifier #4 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
21 ILIM Overcurrent shutdown threshold for V
DD
and VDDNB. A resistor divider from ROSC to GND is typic‐
ally used to develop an appropriate voltage on ILIM.
22 VCCB 5 V supply pin. Tie this pin to VCCA (Pin 1).
23 NB_CS Non-inverting input to the current sense amplifier for the VDDNB regulator
24 NB_CSN Inverting input to the current sense amplifier for the VDDNB regulator
25 VID4 Parallel Voltage ID DAC Input 4. Not used in SVI mode.
26 VID5 Parallel Voltage ID DAC Input 5. Not used in SVI mode.
27 ROSC A resistance from this pin to ground programs the V
DD
and VDDNB oscillator frequencies. This pin
supplies a trimmed output voltage of 2 V.
28 NB_DIFFOUT Output of the differential remote sense amplifier for the VDDNB regulator.
29 NB_OFFSET Input for offset voltage to be added to the VDDNB DAC's output voltage. Ground this pin for zero
VDDNB offset.
30 NB_VS- Inverting input to the differential remote sense amplifier for the VDDNB regulator.
31 NB_VS+ Non-inverting input to the differential remote sense amplifier for the VDDNB regulator.
