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DS1086LU-222+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
3.3V Spread-Spectrum EconOscillator
Maxim Integrated 7
DS1086L
POWER-DOWN CURRENT vs. TEMPERATURE
DS1086L toc09
TEMPERATURE (°C)
POWER-DOWN CURRENT (μA)
603510-15
1.46
1.48
1.50
1.52
1.54
1.56
1.58
1.60
1.62
1.64
1.44
-40 85
SUPPLY CURRENT WITH OUTPUT
DISABLED vs. SUPPLY VOLTAGE
DS1086L toc10
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2.7 3.6
f
O
= 66MHz
SUPPLY CURRENT WITH OUTPUT
DISABLED vs. TEMPERATURE
DS1086L toc11
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
603510-15
2.3
2.4
2.5
2.6
2.7
2.2
-40 85
f
O
= 66MHz
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T
A
= 25°C, unless otherwise noted.)
POWER-DOWN CURRENT vs.
SUPPLY VOLTAGE
DS1086L toc08
SUPPLY VOLTAGE (V)
POWER-DOWN CURRENT (μA)
3.0 3.3
1.1
1.2
1.3
1.4
1.6
1.5
1.7
1.8
1.0
2.7 3.6
3.3V Spread-Spectrum EconOscillator
8 Maxim Integrated
DS1086L
Pin Description
PIN NAME FUNCTION
1 OUT Oscillator Output. The output frequency is determined by the OFFSET, DAC, and prescaler registers.
2 SPRD Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.
3V
CC
Power Supply
4 GND Ground
5OE
Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is
disabled but the master oscillator is still on.
6 PDN
Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master
oscillator is disabled (power-down mode).
7 SDA
2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and
can be wire-ORed with other open-drain or open-collector interfaces.
8 SCL
2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on
falling edges.
DITHERED 260kHz TO
133MHz OUTPUT
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
SPRD
OUT
V
CC
V
CC
V
CC
4.7kΩ 4.7kΩ
V
CC
2-WIRE
INTERFACE
GND
SCL
SDA
PDN
OE
DS1086L
Processor-Controlled Mode
XTL1/OSC1
μP
XTL2/OSC2
DITHERED 130kHz TO
66.6MHz OUTPUT
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS
TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
SPRD
OUT
V
CC
V
CC
V
CC
GND
N.C.
SCL*
SDA*
PDN
OE
DS1086L
Stand-Alone Mode
SPECTRUM COMPARISON
(12OkHz BW, SAMPLE DETECT)
DS1086L fig01
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
51494745
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
43 53
0.5%
NO
SPREAD
fo = 50MHz
DITHER RATE = fo/4096
2%
8%
Figure 1. Clock Spectrum Dither Comparison
MAXIMUM THERMAL VARIATION vs.
MASTER OSCILLATOR FREQUENCY
DS1086L fig02
MASTER FREQUENCY (MHz)
SUPPLY CURRENT (mA)
636036 39 42 48 51 5445 57
-4%
-3%
-2%
-1%
0
1%
2%
3%
-5%
33 66
Figure 2. Temperature Variation Over Frequency
3.3V Spread-Spectrum EconOscillator
Maxim Integrated 9
DS1086L
Detailed Description
A block diagram of the DS1086L is shown in Figure 3.
The internal master oscillator generates a square wave
with a 33.3MHz to 66.6MHz frequency range. The fre-
quency of the master oscillator can be programmed
with the DAC register over a two-to-one range in 5kHz
steps. The master oscillator range is larger than the
range possible with the DAC step size, so the OFFSET
register is used to select a smaller range of frequencies
over which the DAC spans. The prescaler can then be
set to divide the master oscillator frequency by 2
x
(where x equals 0 to 8) before routing the signal to the
output (OUT) pin.
A programmable triangle-wave generator injects an off-
set element into the master oscillator to dither its output
0.5%, 1%, 2%, 4%, or 8%. The dither magnitude is con-
trolled by the JS2, JS1, and JS0 bits in the PRESCALER
word and enabled with the SPRD pin. Futhermore, the
dither rate is controlled by the JS4 and JS3 bits in the
PRESCALER word and determines the frequency of the
dither. The maximum spectral attenuation occurs when
the prescaler is set to 1 and is reduced by 2.7dB for
every factor of 2 that is used in the prescaler. This
happens because the prescaler’s divider function tends
to average the dither in creating the lower frequency.
However, the most stringent spectral emission limits are
imposed on the higher frequencies where the prescaler
is set to a low divider ratio.
The external control input, OE, gates the clock output
buffer. The PDN pin disables the master oscillator and
turns off the clock output for power-sensitive applica-
tions*. On power-up, the clock output is disabled until
power is stable and the master oscillator has generated
512 clock cycles. Both controls feature a synchronous
enable that ensures there are no output glitches when
the output is enabled.
The control registers are programmed through a 2-wire
interface and are used to determine the output frequen-
cy and settings. Once programmed into EEPROM,
since the register settings are NV, the settings only
need to be reprogrammed if it is desired to reconfigure
the device.
SDA
V
CC
SCL
2-WIRE
INTERFACE
V
CC
DAC
OFFSET
EEPROM CONTROL
REGISTERS
PRESCALER
ADDR
RANGE
SPRD
PDN
OUT
OE
DAC
TRIANGLE WAVE
GENERATOR
VOLTAGE-CONTROLLED
OSCILLATOR
PRESCALER
BY 1, 2, 4...256
GND
MASTER
OSCILLATOR
OUTPUT
DITHER SIGNAL
DITHER
CONTROL
FREQUENCY
CONTROL VOLTAGE
DS1086L
Figure 3. Block Diagram
*
The power-down command must persist for at least two out-
put frequency cycles plus 10μs for deglitching purposes.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

DS1086LU-222+

Mfr. #:
Buy DS1086LU-222+
Manufacturer:
Maxim Integrated
Description:
Clock Generators & Support Products SS OSC 22.1184Mhz
Lifecycle:
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