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ISL6401CBZ

P1-P3P4-P6P7-P9P10-P12P13-P13
7
FN9007.8
October 21, 2015
higher, depending on the output current. Total V
CC
current is
the sum of the quiescent V
CC
current and the average
output current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average output current can be
calculated from:
To prevent noise problems, bypass V
CC
to GND with a
ceramic capacitor as close to the V
CC
pin as possible. An
electrolytic capacitor may also be used in addition to the
ceramic capacitor.
Functional Description
Features
The ISL6401 current mode, synchronizable PWM, makes an
ideal choice for low-cost, low-power, multi-output flyback
topology applications with low input-output ripple current
requirements. When configured in a multi-winding flyback
topology, the IC is capable of generating the negative Talk
and Ring voltages required for Ringing Subscriber Line
Interface (RSLIC) power supplies. This approach provides
dual outputs from a single power switch and control IC. Low
current sense voltage and shutdown mode leads to high
efficiency operation. Other features include peak current
mode control, internal soft-start, adjustable current limit,
adjustable frequency and external frequency
synchronization.
Oscillator
The ISL6401 has an internal sawtooth oscillator with a
programmable frequency range of 100kHz to 1MHz, which
can be programmed with a capacitor on the CT pin. (Please
refer to Figure 4 for the capacitance required for a given
frequency.) With a maximum 50% duty cycle operation, the
output switching frequency is half the oscillator frequency.
Implementing Synchronization
The oscillator can be synchronized by an external clock
inserted at the SYNC pin. Program the free running
frequency of the oscillator to be 10% slower than the desired
synchronous frequency. The external clock signal should
have a minimum pulse width of 20ns.
Soft-Start Operation
The ISL6401 features an internal digital soft-start with no
external capacitor required. Soft-start is used to reduce
transformer and output capacitor stress and to reduce the
surge on the input circuits, when the converter action starts.
The considerable capacitance on the output lines should be
charged slowly, so as not to reflect an excessive transient. A
very wide initial pulse could result in saturation of the core
and voltage overshoot on the output, if the inductor current is
allowed to rise to a high value during start-up.
Upon start-up, the peak primary current increments from
1/5th of the value set by R
CS
to the full current limit value in
steps, over 2048 cycles of Fosc or Fsync. Soft-start clamps
the error amplifier output (COMP pin) and the reference
input (non-inverting terminal of the error amplifier) to the
internally generated soft-start voltage. The oscillator
sawtooth waveform is compared to the ramping error
amplifier voltage. This generates GATE pulses of increasing
width that charge the output capacitor(s). With sufficient
output voltage, the clamp on the reference input controls the
output voltage. When the internally generated soft-start
voltage exceeds the FB pin voltage, the output voltage is in
regulation. This method provides a rapid, controlled output
voltage rise. Soft-start is implemented during start-up, after
an overcurrent has cleared, or when exiting shutdown or
undervoltage lock-out (UVLO).
Gate Drive
The ISL6401 is capable of sourcing 1A of peak-drive current.
Separate collector supply (PV
CC
) and power ground (PGnd)
pins help isolate the IC’s analog circuitry from the high power
gate drive noise. To limit the peak current through the IC, an
external resistor is placed between the totem-pole output of
the IC and the gate of the MOSFET. The minimum value of
this resistor is determined by:
Rgate = (Vdd(min) - Vsat) / Igate(peak)
This small series resistor also damps any oscillations
caused by the resonant tank of the parasitic inductances in
the traces of the board and the FET’s input capacitance. A
pull-down resistor is sometimes added to the gate drive to
insure the MOSFET gate does not get charged to its turn-on
threshold during device start-up. Adding a fast-switching
diode and smaller value resistor in parallel with the gate
resistor helps to control the current the IC needs to sink
during turn-off and protects the output stage of the device.
These components also help to reduce turn-off losses, which
tend to dominate the switching losses in discontinuous
current-mode (DCM) converters.
Ground Plane Requirements
Careful layout is essential for correct operation of the device.
A good ground plane must be employed. A unique section of
the ground plane must be designated for high di/dt currents
associated with the output stage. Power ground (PGND) can
be separated from the analog ground (GND) and connected
at a single point. V
CC
should be bypassed directly to PGND
with good high frequency capacitors. The return connection
for input power to the system and the bulk input capacitor
should be connected to the PGND ground plane.
Application Information
Subscriber Line Interface Circuit Requirements
As worldwide demand for inexpensive Voice over Internet
Protocol telephony grows, so will the need for ICs that
enable compatibility between new telephony systems and
older telephones based on analog standards. Old style
telephones require signal and power inputs that are not
generally available on purely digital systems. Analog ring
I
OUT
Qg F=
ISL6401
8
FN9007.8
October 21, 2015
signal generation and off-hook loop current supply are two
analog functions that are performed by Subscriber Line
Interface Circuits (SLICs). A SLIC is the primary interface
between the 4-wire (ground referenced) low voltage switch
environment and the 2 wire (floating) high voltage loop
environment. It performs a number of important functions
including battery feed, overvoltage protection, ringing,
signaling, coding, hybrid balancing and testing.
The Ringing SLIC (RSLIC) typically requires two high
voltage power supply inputs. The first is a tightly regulated
voltage around -24V or -48V for off-hook voice transmission.
The second is a loosely regulated -70 to -100V for ring tone
generation. When the switch hook is released the phone
puts approximately 200 of resistance across the phone
terminals. Once voice transmission begins, the SLIC
requires a lower voltage input to establish a current loop of
approximately 25mA. The loop feeds the 200, protection
resistors, and line resistances within the phone.
ISL6401 Flyback Reference Design
The Typical Application Schematic shows a current mode
power supply using the Intersil ISL6401 in a standard
flyback topology. The IC requires +5V Bias. The application
circuit is intended for wall adapters that power home
gateway/router boxes. This circuit input voltage can be 9V
to 20V with the selected transformer and external
components.
The output voltages are -24V at 120mA and -72V at
120mA. The circuit uses inexpensive transformers to
generate both outputs using a single controller. The
transformer turns ratio is such that 24V appear across each
secondary winding and the primary during the switch off-
time. The remaining secondary windings are stacked in
series to develop -48V. The -48V section is then stacked on
the -24V section to get the -72V. This technique provides
good cross regulation, lowers the voltage rating required
for the output capacitors, and lowers the RMS current,
allowing the use of less expensive output capacitors. Also,
the selection of a transformer with multifilar winding lowers
the leakage inductance and cost. The -24V output is
precisely regulated by feeding back this output to the
controller. The -72V output is derived from the third pair of
windings. Regulation of this output is obtained by the turn’s
ratio of the transformer with -24V output, as well as with
split feedback.
Circuit Element Descriptions
• Transformers T1, MOSFET Q1, Schottky diode D1, D2,
and input capacitor C1 and C2 form the power stage of
the converter. Power resistor R5 senses the switch
current and converts this current into a voltage to be
sensed by the primary side controller feedback
comparator.
• Capacitors C9 to C12 filter out high frequency noise on the
output bus directly at the output diode.
• R7 and C8 provide secondary side snubbing.
• R6 and C7 filter out the leading edge voltage spikes
resulting from the leakage inductance of the transformer.
• C4 sets the switching frequency of the converter.
• C3 is a decoupling capacitor, which should always be a
good quality low-ESR/ESL type capacitor, placed as close
to the IC pins as possible and returned directly to the IC
ground reference.
• The gate drive circuitry can be composed of a small gate
drive resistor, necessary for damping any oscillations
resulting from the input capacitance of Q1 and any
parasitic stray inductance.
• The voltage sense feedback loop is comprised of R4 and
R3. Feedback components R1, C6, and C5 provide the
necessary gain and pole to stabilize the control loop.
Component Selection Guidelines
Power MOSFET
The MOSFET switch is selected to meet the drain to source
voltage stress resulting from the maximum input voltage
(V
IN(max)
), the reflected secondary voltages, equal to the
output voltage (V
OUT
), plus the output diode voltage drop
(V
F
), and the voltage spike due to the leakage inductance,
assumed to be 30% of the input voltage.
Vds (stress) = [(V
IN(max)
) + (N)(Vout +Vf)] + (0.3)(V
IN(max)
)
The switch must also be able to conduct the repetitive peak
primary current as determined by:
Ipeak (primary) = (Vin
min
- Vds) (t
ON(max)
) / Lp
The primary current waveform of a discontinuous mode
flyback converter is triangular in shape, therefore, its root
mean square(rms) current is calculated by:
The chosen device should also have a low R
DS(ON)
value,
because the conduction losses of the device are proportional
to the square of the primary rms current through the device.
Selection of a device that has a peak current rating of at
least three times the peak current usually insures acceptably
low conduction losses.
Pconduction = (I
prms
2
) (R
DS(on)
)
Irms primIPEAKprim 3TONmaxT=
ISL6401
9
FN9007.8
October 21, 2015
Switching losses are the result of overlapping drain current
and source voltage at turn-off. The drain voltage begins to
rise only after the miller capacitance of the device begins to
discharge. This discharging time is a function of the external
gate resistance, Rgate and the gate-to-drain miller charge
Qgd, as shown in the following equation,
T miller = (Qgd)(R
GATE
)/(Vdd-Vth),
where Vth is the turn ON threshold voltage of the gate.
The power loss due to the external capacitance of the
MOSFET also contributes to the total switching losses,
which can be calculated as shown.
During turn on there is no overlap of drain voltage and
current because there is no current in a discontinuous
current mode converter at turn-on. Minimal losses also occur
during the off-time of the FET due to the leakage current.
P
off (time)
= (1 - D
max
)(I
leak
)(V
ds(stress)
)
Output and Input Capacitors
Output capacitors are selected based upon their value,
equivalent series resistance (ESR), equivalent series
inductance and capacitor ripple current rating. The capacitor
value controls the peak-to-peak output ripple voltage at the
switching frequency. Assuming a linear decay of the
capacitor voltage during the off time, during which the
capacitor must supply the load current, the minimum value of
the output capacitor can be calculated as follows,
Cout = [(T- T
ON(max)
)(Iout)] / Vripple),
where Vripple is the acceptable peak-to peak output voltage
ripple. However, there are practical limitations to how low a
single stage output filter can reduce the ripple voltage and
sometimes an extra LC filter stage is necessary. This second
stage filter would also reduce the output high frequency noise.
Parasitic resistance and inductance in the output capacitors
tend to make the ripple voltage much greater than expected,
based upon the above equation. Using capacitors with the
lowest possible ESR and ESL helps reduce high frequency
ripple. The rms ripple current that the output capacitors
experience is not the same as the secondary side rms output
current; it is the AC portion of it. The secondary side rms
current is in the shape of a clipped sawtooth, or trapezoid,
where the output capacitor’s current waveform is in the shape
of right triangle. Therefore, the typical capacitor ripple current
rating the output capacitor must meet is equal to,
where Ipeak (sec) is the peak-secondary current and t
RESET
is equal to the off-time of the switch. The same selection
criteria is used for the input capacitor, keeping in mind these
capacitors must also be rated to handle the maximum input
voltage.
Output Voltage
The output voltage can be set by a feedback resistor divider
network. The output is resistively divided and compared to
the reference voltage. For negative flyback output
applications, the sensed output will be fed to the NFB IN pin.
The sensed voltage in inverted, and this positive voltage is
fed to the FB- inverting input pin of the error amplifier. The
non-inverting input of the error amplifier will be a reference
voltage. So, when FB- is higher than REF voltage, the output
drivers are turned off. The opposite happens when the
resistively divided output voltage falls below the 1.24V
reference voltage.
Output Diode
The output diode in a flyback converter is subject to large
peak and rms current stresses. Schottky diodes are
recommended, because of their low forward-voltage drop and
the virtual absence of minority carrier reverse recovery. The
secondary-side Schottky rectifier was selected to meet the
working peak-reverse voltage, the peak repetitive forward-
current and the average forward-current of the application.
The working peak-reverse voltage Vrev, or blocking voltage, is
calculated according to the following equation:
V
R
= [(V
INmax
+ V
RDSon
) / N ]+ V
OUT
The reflected peak primary current constitutes the peak
repetitive forward-current through the diode. Because all
current to the output capacitors and load must flow through
the diode, the average forward diode current is equal to the
steady-state load current. Power loss in the Schottky is the
sum of the conduction losses and reverse leakage losses.
Conduction losses are calculated using the forward voltage
drop across the diode and the average forward-current.
Reverse leakage losses are dependent upon the reverse
leakage-current, the blocking voltage, and the on-time of
the FET.
Determining the Turns Ratio of the Flyback
Transformer
The turns ratio of the flyback transformer can be calculated
by using the this steady-state volt-second approach:
n = [(V
INmin
- V
DS
)(D
max
)(T)] / [(V
OUT
+ V
F
)(0.8 - D
max
)(T)]
P
switching
F
sw
C
oss
V
DS stress
2
2
--------------------------------------------------------
V
DS stress
I
peak primary
t
miller
+
++
=
Irms Ipeak
Treset
T
-------------------


4
3Treset
T
--------------------------------
–


12
-----------------------------------------------





=
ISL6401
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL6401CBZ

Mfr. #:
Buy ISL6401CBZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers RSLIC PWM 0/+70C 14LD
Lifecycle:
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