40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
AD5379
Rev. B
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FEATURES
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × V
REF
(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (
CLR
pin)
Simultaneous update of DAC outputs (
LDAC
pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options:
Parallel interface
DSP/microcontroller-compatible, 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (
RESET
pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
V
CC
V
DD
V
SS
AGND
RESET
POWER-ON
RESET
DGND LDAC V
BIAS
V
REF
1(+) V
REF
1(–) REFGND A1
VBIAS
DAC 0–1
DAC
REG
0–1
DAC
REG
2
DAC
REG
7
DAC
REG
8–9
INPUT
REG
0–1
INPUT
REG
2
INPUT
REG
7
INPUT
REG
8–9
DAC 2
DAC 7
DAC 8–9
AD5379
DCEN/WR
SYNC/CS
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
DB0
A7
A0
SER/PAR
DIN
SCLK
SDO
FIFOEN
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSY
V
REF
2(+) V
REF
2(–) REFGND A2
CLR
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT39
×4
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
m REG0–1
c REG0–1
m REG2
c REG2
m REG7
c REG7
m REG8–9
c REG8–9
14
/
14
/
14
/
14
/
14
/
14
/
14
/
FIFOSTATE MACHINE
INTERFACE
03165-001
Figure 1.
AD5379—Protected by U.S. Patent No. 5,969,657.
AD5379* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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EVALUATION KITS
AD5379 Evaluation Board
DOCUMENTATION
Data Sheet
AD5379: 40-Channel, 14-Bit, Parallel and Serial Input,
Voltage-Output DAC Data Sheet
Product Highlight
Extending the
dense
DAC™ Multichannel D/As
REFERENCE MATERIALS
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
AD5379 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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AD5379
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 3
Specifications ..................................................................................... 4
AC Characteristics ........................................................................ 5
Timing Characteristics ..................................................................... 6
Serial Interface .............................................................................. 6
Parallel Interface ........................................................................... 9
Absolute Maximum Ratings .......................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Terminology .................................................................................... 15
Typical Performance Characteristics ........................................... 16
Functional Description .................................................................. 18
DAC Architecture—General ..................................................... 18
Channel Groups .......................................................................... 18
Transfer Function ....................................................................... 18
V
BIAS
Function ............................................................................. 19
Reference Selection .................................................................... 19
Calibration ................................................................................... 20
Clear Function ............................................................................ 20
BUSY
and
LDAC
Functions...................................................... 20
FIFO vs. Non-FIFO Operation ................................................. 21
BUSY
Input Function ................................................................ 21
Power-On Reset Function ......................................................... 21
RESET
Input Function .............................................................. 21
Increment/Decrement Function .............................................. 21
Interfaces.......................................................................................... 22
Parallel Interface ......................................................................... 22
Serial Interface ............................................................................ 22
Data Decoding ................................................................................ 24
Address Decoding .......................................................................... 25
Power Supply Decoupling ............................................................. 26
Power-On .................................................................................... 26
Typical Application Circuit ........................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/09—Rev. A t o Rev. B
Changes to Table 14 ........................................................................ 24
1/05—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Change to Transfer Function Equation ....................................... 18
4/04—Revision 0: Initial Version

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