AD5379
Rev. B | Page 24 of 28
DATA DECODING
The AD5379 contains a 14-bit data bus, DB13 to DB0. Depend-
ing on the values of REG1 and REG0, this data is loaded into
the addressed DAC input register(s), offset (c) register(s), gain
(m) register(s), or the special function register.
Table 12. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0 DAC Output
11 1111 1111 1111 (16383/16384) V
REF
(+) V
11 1111 1111 1110 (16382/16384) V
REF
(+) V
10 0000 0000 0001 (8193/16384) V
REF
(+) V
10 0000 0000 0000 (8192/16384) V
REF
(+) V
01 1111 1111 1111 (8191/16384) V
REF
(+) V
00 0000 0000 0001 (1/16384) V
REF
(+) V
00 0000 0000 0000 0 V
Table 13. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0 Offset (LSB)
11 1111 1111 1111 +8191
11 1111 1111 1110 +8190
10 0000 0000 0001 +1
10 0000 0000 0000 +0
01 1111 1111 1111 −1
00 0000 0000 0001 −8191
00 0000 0000 0000 −8192
Table 14. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB1 Gain
1 1111 1111 1111 8192/8192
1 1111 1111 1110 8191/8192
1 0000 0000 0001 4098/8192
1 0000 0000 0000 4097/8192
0 1111 1111 1111 4096/8192
0 0000 0000 0001 2/8192
0 0000 0000 0000 1/8192
Table 15. Special Function Data Format (REG1 = 0, REG0 = 0)
DB13 to DB0 Increment/Decrement Step (LSB)
00000 10 1111111 +127
00000 10 0000111 +7
00000 10 0000001 +1
00000 X0 0000000 0
00000 00 0000001 −1
00000 00 0000111 −7
00000 00 1111111 −128
Table 16. Soft Reset (REG1 = 0, REG0 = 0)
DB13 to DB0 DAC Output
11 1111 1111 1111 REFGND
AD5379
Rev. B | Page 25 of 28
ADDRESS DECODING
The AD5379 contains an 8-bit address bus, A7 to A0. This
address bus allows each DAC input register (x1), each offset (c)
register, and each gain (m) register to be individually updated.
The REG1 and REG0 bits in the special function register (SFR)
(see Table 9) show the decoding for data, offset, and gain
registers. Note that when all 40 DAC channels are selected,
Address Bit A3 to Address Bit A0 are ignored.
Table 17. DAC Group Addressing
A7 A6 A5 A4 Group A3 A2 A1 A0 Data/Offset/Gain/INC-DEC Register
0 0 0 0 All 40 DACs 0 0 0 0 Register 0
0 0 0 1 Group A 0 0 0 1 Register 1
0 0 1 0 Group B 0 0 1 0 Register 2
0 0 1 1 Groups A, B 0 0 1 1 Register 3
0 1 0 0 Group C 0 1 0 0 Register 4
0 1 0 1 Groups A, C 0 1 0 1 Register 5
0 1 1 0 Groups B, C 0 1 1 0 Register 6
0 1 1 1 Groups A, B, C 0 1 1 1 Register 7
1 0 0 0 Group D 1 0 0 0 Register 8
1 0 0 1 Groups A, D 1 0 0 1 Register 9
1 0 1 0 Groups B, D
1 0 1 1 Groups A, B, D
1 1 0 0 Groups C, D
1 1 0 1 Groups A, C, D
1 1 1 0 Groups B, C, D
1 1 1 1 Groups A, B, C, D
AD5379
Rev. B | Page 26 of 28
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5379 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5379 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (V
SS
, V
DD
, V
CC
), it is recom-
mended to tie these pins together and to decouple each
supply once.
The AD5379 should have ample supply decoupling of 10 μF in
parallel with 0.1 μF on each supply located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-
tor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal
logic switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5379 to avoid
noise coupling. The power supply lines of the AD5379 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. It is essential to mini-
mize noise on all V
REF
(+) and V
REF
(−) lines. The V
BIAS
pin should
be decoupled with a 10 nF capacitor to AGND.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the CSPBGA package and to avoid a point load on the
surface of this package during the assembly process.
POWER-ON
An on-chip power supply monitor makes the AD5379 robust to
power sequencing. The supply monitor powers up the analog
section after (V
DD
− V
SS
) is greater than 7 V (typical). The
output buffers power-up in
CLR
mode forced to the DUTGND
potential, even if V
CC
remains at 0 V. After V
SS
is applied, the
analog circuitry powers up, and the buffered DAC output level
settles linearly within the supply range.

EVAL-AD5379EBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
BOARD EVALUATION FOR AD5379
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet