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AD7244JNZ

P1-P3P4-P6P7-P9P10-P12
AD7242/AD7244
REV. A
–4–
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (J, K, A, B Versions) (S Version) Units Conditions/Comments
t
1
50 50 ns min TFS to TCLK Falling Edge
t
2
75 100 ns min TCLK Falling Edge to TFS
t
3
3
150 200 ns min TCLK Cycle Time
t
4
30 40 ns min Data Valid to TCLK Setup Time
t
5
75 100 ns min Data Valid to TCLK Hold Time
t
6
40 40 ns min LDAC Pulse Width
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-
age level of 1.6 V.
2
See Figure 6.
3
TCLK Mark/Space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
REF INA, REF INB to AGND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
J, K Versions
AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
(V
DD
= +5 V 6 5%, V
SS
= –5 V 6 5%, AGND = DGND = 0 V)
PIN CONFIGURATIONS
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 550 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIP
SOIC
AD7242/AD7244
REV. A
–5–
AD7242/AD7244 PIN FUNCTION DESCRIPTION
DIP
Pin No. Mnemonic Description
1
LDACA Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-
ing edge of this signal. If
LDACA is hard-wired low, data is transferred from input Latch A to DAC
Latch A on the sixteenth falling edge of TCLKA after
TFSA goes low.
2
TFSA Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA
data with serial data expected after the falling edge of this signal.
3 DTA Transmit Data, Logic Input. This is the data input which is used in conjunction with
TFSA and
TCLKA to transfer serial data to input Latch A.
4 TCLKA Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA
when
TFSA is low.
5 DGND Digital Ground. Both DGND pins for the device must be tied together at the device.
6 TP1 Test Pin 1. Used when testing the device. Do not connect anything to this pin.
7V
DD
Positive Power Supply, 5 V ± 5%. Both V
DD
pins for the device must be tied together at the device.
8 AGND Analog Ground. Both AGND pins for the device must be tied together at the device.
9V
OUTB
Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INB = +3 V.
10 V
SS
Negative Power Supply, –5 V ± 5%. Both V
SS
pins for the device must be tied together at the device.
11 TP2 Test Pin 2. Used when testing the device. Do not connect anything to this pin.
12 REF INB DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally
buffered before being applied to DACB. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
13
LDACB Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-
ing edge of this signal. If
LDACB is hard-wired low, data is transferred from input Latch B to DAC
Latch B on the sixteenth falling edge of TCLKB after
TFSB goes low.
14
TFSB Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB
data with serial data expected after the falling edge of this signal.
15 DTB Transmit Data, Logic Input. This is the data input used in conjunction with
TFSB and TCLKB to
transfer serial data to input Latch B.
16 TCLKB Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB
when
TFSB is low.
17 DGND Digital Ground. Both DGND pins for the device must be tied together at the device.
18 TP3 Test Pin 3. Used when testing the device. Do not connect anything to this pin.
19 V
DD
Positive Power Supply, 5 V ± 5%. Both V
DD
pins for the device must be tied together at the device.
20 AGND Analog Ground. Both AGND pins for the device must be tied together at the device.
21 V
OUTA
Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INA = +3 V.
22 V
SS
Negative Power Supply, –5 V ± 5%. Both V
SS
pins for the device must be tied together at the device.
23 REF OUT Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be
connected to both REF INA and REF INB. The external load capability of the reference is 500 µA.
24 REF INA DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally
buffered before being applied to DACA. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
AD7242/AD7244
REV. A
–6–
CIRCUIT DESCRIPTION
The AD7242/AD7244 contains two 12-bit/14-bit D/A convert-
ers, each with an output buffer amplifier. The part also contains
a reference input buffer amplifier for each DAC, and an on-chip
3 V reference.
D/A Section
The AD7242/AD7244 contains two 12-bit/14-bit voltage mode
D/A converters, each consisting of highly stable thin-film resistors
and high speed single-pole, double-throw switches. The simplified
circuit diagram for the DAC section is shown in Figure 1. The
three MSBs of the data word are decoded to drive the seven
switches A-G. On the AD7242, the 9 LSBs switch a
9-bit R-2R ladder structure while on the AD7244, the 11 LSBs
switch an 11-bit R-2R ladder structure. The output voltage
from this converter has the same polarity as the reference
voltage, REF IN.
The REF IN voltage is internally buffered by a unity gain
amplifier before being applied to the D/A converters and the
bipolar bias circuitry. The D/A converter is configured and
scaled for a 3 V reference, and the device is tested with 3 V
applied to REF IN. Operating the AD7242/AD7244 at refer-
ence voltages outside the ±5% tolerance range may result in
degraded performance from the part.
Figure 1. DAC Ladder Structure
Internal Reference
The on-chip reference is a temperature-compensated buried
Zener reference that is factory trimmed for 3 V ± 10 mV. The
reference can be used to provide both the reference voltage for
the two D/A converters and the bipolar biasing circuitry. This is
achieved by connecting REF OUT to REF INA and REF INB.
The reference voltage can also be used for other components
and is capable of providing up to 500 µA to an external load.
The maximum recommended capacitance on the reference
output pin for normal operation is 50 pF. If the reference
output is required to drive a capacitive load greater than 50 pF,
a 200 Ω resistor should be placed in series with the capacitive
load. Decoupling the REF OUT pin with a series 200 Ω resistor
and a parallel combination of a 10 µF tantalum capacitor and a
0.1 µF ceramic capacitor as in Figure 2 reduces the noise
spectral density of the reference (see Figure 4). Using this
decoupling scheme to generate the reference voltage for REF
INA and REF INB gives a channel-to-channel isolation number
of 110 dB (connecting REF OUT directly to REF INA and
REF INB gives 80 dB). The channel-to-channel isolation is 110
dB using an external reference.
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7242/AD7244
reference inputs. Figure 3 shows how the AD586 reference can
be conditioned to provide the 3 V reference required by the
AD7242/AD7244 reference inputs.
Figure 2. Circuit Connection for REF OUT with an External
Capacitive Load of Greater Than 50 pF
Figure 3. AD586 Driving AD7242/AD7244 Reference Inputs
P1-P3P4-P6P7-P9P10-P12

AD7244JNZ

Mfr. #:
Buy AD7244JNZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12/14 BIT 3V Zener Ref IC
Lifecycle:
New from this manufacturer.
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