AD7244JNZ Datasheet AD7244JNZ, AD7244JRZ, AD7244AQ | P7-P9

AD7242/AD7244

REV. A

–7–

Output Amplifier

The outputs from each of the voltage-mode DACs are buffered

by a noninverting amplifier. The buffer amplifier is capable of

developing ±3 V across a 2 kΩ and 100 pF load to ground, and

can produce 6 V peak-to-peak sine wave signals to a frequency

of 20 kHz. The output is updated on the falling edge of the

respective

LDAC input. The output voltage settling time, to

within 1/2 LSB of its final value, is typically less than 2 µs for

the AD7242 and 2.5 µs for the AD7244.

The small signal (200 mV p-p) bandwidth of the output buffer

amplifier is typically 1 MHz. The output noise from the

amplifier is low, with a figure of 30 nV/√

Hz at a frequency of

1 kHz. The broadband noise from the amplifier exhibits a

typical peak-to-peak figure of 150 µV for a 1 MHz output

bandwidth. Figure 4 shows a typical plot of noise spectral

density versus frequency for the output buffer amplifier and for

the on-chip reference (including and excluding the decoupling

components).

Figure 4. Noise Spectral Density vs. Frequency

TRANSFER FUNCTION

The basic circuit configuration for the AD7242/AD7244 is

shown in Figure 5. Table I and Table II show the ideal input

code to output voltage relationship for the AD7242 and

AD7244 respectively. Input coding for the AD7242/AD7244 is

2s complement.

Figure 5. Basic Connection Diagram

For the AD7242, the output voltage can be expressed in terms

of the input code, N, using the following relationship:

OUT

2 •N • REF IN

4096

where –2048 ≤ N ≤ +2047

For the AD7244, the output voltage can be expressed in terms

of the input code, N, using the following relationship:

OUT

2 •N • REF IN

16384

where –8192 ≤ N ≤ +8191

Table I. AD7242 Ideal Input/Output Code Table Code

DAC Latch Contents

MSB LSB Analog Output, V

OUT

01 11 1111 1111 +2.998535 V

01 11 1111 1110 +2.99707 V

00 00 0000 0001 +0.001465 V

00 00 0000 0000 0 V

11 11 1111 1111 –0.001465 V

10 00 0000 0001 –2.998535 V

10 00 0000 0000 –3 V

*Assuming REF IN = +3 V.

Table II. AD7244 Ideal Input/Output Code Table Code

DAC Latch Contents

MSB LSB Analog Output, V

OUT

01 1111 1111 1111 +2.999634 V

01 1111 1111 1110 +2.99268 V

00 0000 0000 0001 +0.000366 V

00 0000 0000 0000 0 V

11 1111 1111 1111 –0.000366 V

10 0000 0000 0001 –2.999634 V

10 0000 0000 0000 –3 V

*Assuming REF IN = +3 V.

AD7242/AD7244

REV. A

–8–

TIMING AND CONTROL

Communication with the AD7242/AD7244 is via six serial logic

inputs. These consist of separate serial clocks, word framing and

data lines for each DAC. DAC updating is controlled by two

digital inputs:

LDACA for updating V

OUTA

and LDACB for

updating V

OUTB

. These inputs can be asserted independently of

the microprocessor by an external timer when precise updating

intervals are required. Alternatively, the

LDACA and LDACB

inputs can be driven from a decoded address bus allowing the

microprocessor control over DAC updating as well as data

communication to the AD7242/AD7244 input latches.

The AD7242/AD7244 contains two latches per DAC, an input

latch and a DAC latch. Data must be loaded to the input latch

under the control of TCLKA,

TFSA and DTA for input Latch

A and TCLKB,

TFSB and DTB for input Latch B. Data is then

transferred from input Latch A to DAC Latch A under the control

of the

LDACA signal, while LDACB controls the loading of DAC

Latch B from input Latch B. Only the data held in the DAC

latches determines the analog outputs of the AD7242/AD7244.

Data is loaded to the input latches under control of the respec-

tive TCLK,

TFS and DT signals. The AD7242/AD7244

expects a 16-bit stream of serial data on its DT inputs. Data

must be valid on the falling edge of TCLK. The

TFS input

provides the frame synchronization signal that tells the AD7242/

AD7244 that valid serial data will be available on the DT input

for the next 16 falling edges of TCLK. Figure 6 shows the

timing diagram for operation of either of the two serial input

ports on the part.

Although 16 bits of data are clocked into the input latch, only

12 bits are transferred into the DAC latch for the AD7242 and

14 bits are transferred for the AD7244. Therefore, 4 bits in the

AD7242 data stream and 2 bits in the AD7244 data stream are

don’t cares since their value does not affect the DAC latch data.

The bit positions are the don’t cares followed by the DAC data

starting with the MSB (see Figure 6).

The respective

LDAC signals control the transfer of data to the

respective DAC latches. Normally, data is loaded to the DAC

latch on the falling edge of

LDAC. However, if LDAC is held

low, serial data is loaded to the DAC latch on the sixteenth

falling edge of TCLK. If

LDAC goes low during the loading of

serial data to the input latch, no DAC latch update takes place

on the falling edge of

LDAC. If LDAC stays low until the serial

transfer is completed, then the update takes place on the sixteenth

falling edge of TCLK. If

LDAC returns high before the serial

data transfer is completed, no DAC latch update takes place.

If seventeen or more TCLK edges occur while

TFS is low, the

seventeenth (and beyond) clock edges are ignored, i.e., no

further data is clocked into the input latch after the sixteenth

TCLK edge following a falling edge on

TFS.

Figure 6. AD7242/AD7244 Timing Diagram

AD7242/AD7244

REV. A

–9–

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD7242/AD7244 is via a

serial bus that uses standard protocol compatible with DSP

processors and microcontrollers. The communication interface

consists of a separate transmit section for each of the DACs.

Each section has a clock signal, a data signal and a frame or

strobe pulse.

Figures 7 through 11 show the AD7242/AD7244 configured

for interfacing to a number of popular DSP processors and

microcontrollers.

AD7242/AD7244 to ADSP-2101/ADSP-2102 Interface

Figure 7 shows a serial interface between the AD7242/AD7244

and the ADSP-2101/ADSP-2102 DSP processor. The ADSP-

2101/ADSP-2102 has two serial ports and, in the interface

shown, both serial ports are used, one for each DAC. Both serial

ports do not have to be used; in the case where only one serial

port is used, an extra line (DACA/

DACB as shown in the other

serial interfaces) would have to decode the one

TFS line to

provide

TFSA and TFSB lines for the AD7242/AD7244.

Figure 7. AD7242/AD7244 to ADSP-2101/ADSP-2102

Interface

The three serial lines of the first serial port, SPORT1, of the

ADSP-2101/ADSP-2102 connect directly to the three serial

input lines of DACA of the AD7242/AD7244. The three serial

lines of SPORT2 connect directly to the three serial lines on the

DACB serial input port. Data from the ADSP-2101/ADSP-2102 is

valid on the falling edge of SCLK. A common LDAC signal is

used to drive the

LDACA and LDACB inputs. This is shown to

be generated from a timer or clock recovery circuit but another

control or address line of the ADSP-2101/ADSP-2102 could be

used to drive these inputs. Alternatively, the

LDACA and

LDACB inputs of the AD7242/AD7244 could be hardwired

low; in this case the update of the DAC latches and analog

outputs takes place on the 16th falling edge of SCLK (after the

respective

TFS signal goes low).

AD7242/AD7244 to DSP56000 Interface

A serial interface between the AD7242/AD7244 and the

DSP56000 is shown in Figure 8. The DSP56000 is configured

for normal mode, asynchronous operation with gated clock. It is

also set up for a 16-bit word with SCK and SC2 as outputs and

the FSL control bit set to a 0. SCK is internally generated on

the DSP56000 and applied to both the TCLKA and TCLKB

inputs of the AD7242/AD7244. Data from the DSP56000 is

valid on the falling edge of SCK. The serial data line, STD

drives the DTA and DTB serial input data lines of the

AD7242/AD7244.

The SC2 output provides the framing pulse for valid data. This

is an active high output and is gated with a DACA/

DACB

control line before being applied to the

TFSA and TFSB inputs

of the AD7242/AD7244. The DACA/

DACB line determines

which DAC serial data is to be transferred to, i.e., which

TFS

line is active when SC2 is active.

As in the previous interface, a common

LDAC input is shown

driving the

LDACA and LDACB inputs of the AD7242/AD7244.

Once again, these

LDAC inputs could be hardwired low, in

which case V

OUTA

or V

OUTB

will be updated on the sixteenth

falling edge of SCK after the

TFSA or TFSB input goes low.

Figure 8. AD7242/AD7244 to DSP56000 Interface

P1-P3 P4-P6 P7-P9 P10-P12

AD7244JNZ

Mfr. #:

Buy AD7244JNZ

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 12/14 BIT 3V Zener Ref IC

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AD7244JNZ

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