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LTC4449EDCB#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P14
LTC4449
7
4449fa
OPERATION
TIMING DIAGRAM
Figure 1. Three-State Input Operation
V
IL(BG)
V
IL(TG)
V
IL(BG)
90%
IN
TG
BG
90%
10%
t
r(TG)
t
pLH(TG)
10%
t
r(BG)
4449 TD
t
f(BG)
t
f(TG)
t
pLH(BG)
t
pHL(BG)
t
pHL(TG)
Overview
The LTC4449 receives a ground-referenced, low voltage
digital input signal to drive two N-channel power MOSFETs
in a synchronous power supply confi guration. The gate
of the low side MOSFET is driven either to V
CC
or GND,
depending on the state of the input. Similarly, the gate of
the high side MOSFET is driven to either BOOST or TS by
a supply bootstrapped off of the switch node (TS).
Input Stage
The LTC4449 employs a unique three-state input stage with
transition thresholds that are proportional to the V
LOGIC
supply. The V
LOGIC
supply can be tied to the controller
IC’s power supply so that the input thresholds will match
those of the controller’s output signal. Alternatively, V
LOGIC
can be tied to V
CC
to simplify routing. An internal voltage
regulator in the LTC4449 limits the input threshold values
for V
LOGIC
supply voltages greater than 5V.
The relationship between the transition thresholds and
the three input states of the LTC4449 is illustrated in
Figure 1. When the voltage on IN is greater than the
threshold V
IH(TG)
, TG is pulled up to BOOST, turning the
high side MOSFET on. This MOSFET will stay on until IN
falls below V
IL(TG)
. Similarly, when IN is less than V
IH(BG)
,
BG is pulled up to V
CC
, turning the low side (synchronous)
MOSFET on. BG will stay high until IN increases above
the threshold V
IL(BG)
.
The thresholds are positioned to allow for a region in which
both BG and TG are low. An internal resistive divider will
pull IN into this region if the signal driving the IN pin goes
into a high impedance state.
One application of this three-state input is to keep both of
the power MOSFETs off while an undervoltage condition
exists on the controller IC power supply. This can be
accomplished by driving the IN pin with a logic buffer
that has an enable pin. With the enable pin of the buffer
tied to the power good pin of the controller IC, the logic
buffer output will remain in a high impedance state until the
controller confi rms that its supply is not in an undervoltage
state. The three-state input of the LTC4449 will therefore
pull IN into the region where TG and BG are low until the
controller has enough voltage to operate predictably.
TG HIGH
TG HIGH
V
IH(TG)
V
IL(BG)
V
IL(TG)
V
IH(BG)
IN
TG LOW
TG LOW
BG LOW
BG HIGH
4449 F01
BG LOW
BG HIGH
LTC4449
8
4449fa
OPERATION
Rise/Fall Time
Since the power MOSFETs generally account for the
majority of power loss in a converter, it is important to
quickly turn them on and off, thereby minimizing the
transition time and power loss. The LTC4449’s peak pull-
up current of 3.2A for both BG and TG produces a rapid
turn-on transition for the MOSFETs. This high current is
capable of driving a 3nF load with an 8ns rise time.
It is also important to turn the power MOSFETs off quickly
to minimize power loss due to transition time; however,
an additional benefi t of a strong pull-down on the driver
outputs is the prevention of cross-conduction current. For
example, when BG turns the low side power MOSFET off and
TG turns the high side power MOSFET on, the voltage on
the TS pin will rise to V
IN
very rapidly. This high frequency
positive voltage transient will couple through the C
GD
capacitance of the low side power MOSFET to the BG pin.
If the BG pin is not held down suffi ciently, the voltage on
the BG pin will rise above the threshold voltage of the low
side power MOSFET, momentarily turning it back on. As
a result, both the high side and low side MOSFETs will be
conducting, which will cause signifi cant cross-conduction
current to fl ow through the MOSFETs from V
IN
to ground,
thereby introducing substantial power loss. A similar effect
occurs on TG due to the C
GS
and C
GD
capacitances of the
high side MOSFET.
The hysteresis between the corresponding V
IH
and V
IL
voltage levels eliminates false triggering due to noise
during switch transitions; however, care should be taken
to keep noise from coupling into the IN pin, particularly
in high frequency, high voltage applications.
Undervoltage Lockout
The LTC4449 contains undervoltage lockout detectors that
monitor both the V
CC
and V
LOGIC
supplies. When V
CC
falls
below 3.04V or V
LOGIC
falls below 2.65V, the output pins
BG and TG are pulled to GND and TS, respectively. This
turns off both of the external MOSFETs. When V
CC
and
V
LOGIC
have adequate supply voltage for the LTC4449 to
operate reliably, normal operation will resume.
Adaptive Shoot-Through Protection
Internal adaptive shoot-through protection circuitry
monitors the voltages on the external MOSFETs to ensure
that they do not conduct simultaneously. The LTC4449
does not allow the bottom MOSFET to turn on until the
gate-source voltage on the top MOSFET is suffi ciently
low, and vice-versa. This feature improves effi ciency by
eliminating cross-conduction current from fl owing from
the V
IN
supply through the MOSFETs to ground during a
switch transition.
Output Stage
A simplifi ed version of the LTC4449’s output stage is
shown in Figure 2. The pull-up device on both the BG and
TG outputs is an NPN bipolar junction transistor (Q1 and
Q2) in parallel with a low resistance P-channel MOSFET
(P1 and P2). This powerful combination rapidly pulls the
BG and TG outputs to their positive rails (V
CC
and BOOST,
respectively). Both BG and TG have N-channel MOSFET
pull-down devices (N1 and N2) which pull BG and TG
down to their negative rails, GND and TS. An additional
NPN bipolar junction transistor (Q3) is present on BG
to increase its pull-down drive current capacity. The
rail-to-rail voltage swing of the BG and TG output pins
is important in driving external power MOSFETs, whose
R
DS(ON)
is inversely proportional to its gate overdrive
voltage (V
GS
– V
TH
).
BOOST
LTC4449
TG
TS
C
GS
C
GD
HIGH SIDE
POWER
MOSFET
V
IN
V
CC
BG
N2
P2
Q2
GND
C
GS
4449 F02
C
GD
LOW SIDE
POWER
MOSFET
LOAD
INDUCTOR
Q3
N1
P1
Q1
Figure 2. Capacitance Seen by BG and TG During Switching
LTC4449
9
4449fa
APPLICATIONS INFORMATION
OPERATION
The LTC4449’s powerful parallel combination of the
N-channel MOSFET (N2) and NPN (Q3) on the BG
pull-down generates a phenomenal 4ns fall time on BG
while driving a 3nF load. Similarly, the 0.8 pull-down
Power Dissipation
To ensure proper operation and long-term reliability,
the LTC4449 must not operate beyond its maximum
temperature rating. Package junction temperature can
be calculated by:
T
J
= T
A
+ (P
D
)(θ
JA
)
where:
T
J
= junction temperature
T
A
= ambient temperature
P
D
= power dissipation
θ
JA
= junction-to-ambient thermal resistance
Power dissipation consists of standby, switching and
capacitive load power losses:
P
D
= P
DC
+ P
AC
+ P
QG
where:
P
DC
= quiescent power loss
P
AC
= internal switching loss at input frequency f
IN
P
QG
= loss due turning on and off the external
MOSFET with gate charge Q
G
at frequency f
IN
The LTC4449 consumes very little quiescent current. The
DC power loss at V
LOGIC
= 5V and V
CC
= 5V is only (730A
+ 600µA)(5V) = 6.65mW.
At a particular switching frequency, the internal power loss
increases due to both AC currents required to charge and
discharge internal nodal capacitances and cross-conduc-
tion currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Input Frequency.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
pure capacitive loads C
LOAD
on TG and BG at switching
frequency fi n, the load losses would be:
P
CLOAD
= (C
LOAD
)(f
IN
)[(V
BOOST – TS
)
2
+ (V
CC
)
2
]
In a typical synchronous buck confi guration, V
BOOST
– TS
is equal to V
CC
– V
D
, where V
D
is the forward voltage drop
of the external Schottky diode between V
CC
and BOOST.
If this drop is small relative to V
CC
, the load losses can
be approximated as:
P
CLOAD
≈ 2(C
LOAD
)(f
IN
)(V
CC
)
2
Unlike a pure capacitive load, a power MOSFET’s gate
capacitance seen by the driver output varies with its V
GS
voltage level during switching. A MOSFET’s capacitive load
power dissipation can be calculated using its gate charge,
Q
G
. The Q
G
value corresponding to the MOSFET’s V
GS
value (V
CC
in this case) can be readily obtained from the
manufacturer’s Q
G
vs V
GS
curves. For identical MOSFETs
on TG and BG:
P
QG
≈ 2(V
CC
)(Q
G
)(f
IN
)
To avoid damaging junction temperatures due to power
dissipation, the LTC4449 includes a temperature monitor
that will pull BG and TG low if the junction temperature
exceeds 160°C. Normal operation will resume when the
junction temperature cools to less than 135°C.
MOSFET (N1) on TG results in a rapid 7ns fall time with
a 3nF load. These powerful pull-down devices minimize
the power loss associated with MOSFET turn-off time and
cross-conduction current.
P1-P3P4-P6P7-P9P10-P12P13-P14

LTC4449EDCB#TRPBF

Mfr. #:
Buy LTC4449EDCB#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Hi Speed Sync N-Ch MOSFET Drvr
Lifecycle:
New from this manufacturer.
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