4-Bit, 2:1, Single-Ended Multiplexer
83054I-01
Datasheet
©2015 Integrated Device Technology, Inc December 15, 20151
GENERAL DESCRIPTION
The 83054I-01 is a 4-bit, 2:1, Single-ended Multiplexer and a
member of the family of High Performance Clock Solutions from
IDT. The 83054I-01 has two selectable single-ended clock inputs
and four single-ended clock outputs. The output has a V
DDO
pin
which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal
for use in voltage translation applications. An output enable pin
places the output in a high impedance state which may be useful
for testing or debug. Possible applications include systems with up
to four transceivers which need to be independently set for different
rates. For example, a board may have four transceivers, each of
which need to be independently confi gured for 1 Gigabit Ethernet
or 1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Error
Correction) or non-FEC rates. The device operates up to 250MHz
and is packaged in a 16 TSSOP.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
• Four-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15Ω (V
DDO
= 3.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3.2ns (maximum), V
DD
= V
DDO
= 3.3V
• Input skew: 170ps (maximum), V
DD
= V
DDO
= 3.3V
• Output skew: 90ps (maximum), V
DD
= V
DDO
= 3.3V
• Part-to-part skew: 800ps (maximum), V
DD
= V
DDO
= 3.3V
• Additive phase jitter, RMS at 155.52MHz, (12kHz – 20MHz):
0.18ps (typical)
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
SEL0
CLK0
CLK1
SEL3
OE
Q0
Q3
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
SEL3
Q3
V
DDO
GND
Q2
SEL2
CLK1
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0
Q0
V
DDO
GND
Q1
SEL1
CLK0
OE
83054I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
