MR48V256ATAZBARL

PEDR48V256A-06
Issue Date: Oct. 17, 2011
MR48V256A
32,768-Word 8-Bit FeRAM (Ferroelectric Random Access Memory)
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GENERAL DESCRIPTION
The MR48V256A is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. Unlike SRAMs, this device, whose cells are
nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and
programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle
time can be equal to the read cycle time and the power consumption during a write can be reduced significantly.
The MR48V256A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 10
12
cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 32,768-word 8-bit configuration
A single 3.3 V 0.3 V power supply
Read access time: 70 ns (Max.)
Write enable time: 70 ns (Min.)
Random read/write cycle time 150 ns (Min.)
• Read/write tolerance 10
12
cycles/bit
Data retention 10 years
Guaranteed operating temperature range 40 to 85C (Extended temperature version)
• Package options:
28-pin plastic TSOPI (TSOP(1)28-08134-0.55-ZK)
PRODUCT FAMILY
Access Time
Family
Relative to CE Relative to OE
Read/Write
Cycle Time
Package
MR48V256A 70ns 40ns 150ns 28pin TSOPI
PEDR48V256A-06
MR48V256A
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PIN CONFIGURATION
Note:
Signal names that end with # indicate that the pins are negative-true logic.
28-pin plastic TSOPI
OE#
A11
A9
A8
A13
WE#
VCC
A14
A12
A7
A6
A5
A4
A3
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
MR48V256A-XX
PEDR48V256A-06
MR48V256A
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PIN DESCRIPTIONS
Pin Name Description
CE#
Chip enable (input, negative logic)
Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
OE#
Output enable (input, negative logic)
The FeRAM is in read mode when the FeRAM is active and this pin is low, and data is
output after the specified time.
WE#
Write enable (input, negative logic)
The FeRAM is in write mode when the FeRAM is active and this pin is low, and data is
capture at the timing of WE#="H" or CE#="H", whichever is earlier.
A14 to A0
Address (input)
The FeRAM captures an address at the timing when CE#="L" is established.
DQ7 to DQ0
3-state data bus (input/output)
Outputs data in the read mode, and captures data in the write mode.
V
CC
, V
SS
Power supply
Apply the specified voltage to V
CC
. Connect V
SS
to ground.
TRUTH TABLE
Operating Mode CE# WE#
Standby Mode H X
Address Latched X
Read Mode
L H
Write Mode
L

MR48V256ATAZBARL

Mfr. #:
Manufacturer:
Description:
IC FRAM 256K PARALLEL 28TSOP I
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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