MR48V256ATAZBARL

PEDR48V256A-06
MR48V256A
10/12
CE-Only Cycle
Note: OE# = “H”, WE# = “H”, DQ = High-Z
Power-On and Power-Off Characteristics
(Under recommended operating conditions)
Parameter Symbol Min. Max. Unit Note
Power-On CE# High Hold Time
t
VHEL
50 s 1, 2
Power-Off CE# High Hold Time
t
EHVL
100 ns 1
Power-On Interval Time
t
VLVH
1 s 2
Notes:
1. To prevent an erroneous operation, be sure to maintain CE#="H", and set the FeRAM in an inactive state
(standby mode) before and after power-on and power-off.
2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up
from 0 V.
3. Enter all signals at the same time as power-on or enter all signals after power-on.
Power-On and Power-Off Sequences
An
CE
#
A
ddress Valid
Invalid Address In
t
AVEL
t
ELAX
t
EHEL
t
ELEH
0
V
V
IL
Max.
V
CC
Min.
V
CC
V
IH
Min.
CE#
0V
V
IL
Max.
V
CC
Min.
V
CC
V
IH
Min.
CE#
t
VHEL
t
VLVH
t
EHVL
PEDR48V256A-06
MR48V256A
11/12
REVISION HISTORY
Page
Document No. Date
Previous
Edition
Current
Edition
Description
PEDR48V256A-01 Mar. 30, 2010 Preliminary edition 1 from PJDR48V256A-05
1 1 Package code name
PEDR48V256A-02 Aug. 26, 2010
1,4,5 1,4,5
Input Voltage
2.0/0.8 Vcc x 0.8 / Vcc x 0.2
PEDR48V256A-03 Dec. 02, 2010 4 4 Input Voltage VIL Vcc x 0.2 Vcc x 0.15
PEDR48V256A-04 Mar. 04, 2011 1,2,4 1,2,4
Pin name VDD VCC
tem
p
erature version Extended version
PEDR48V256A-05 Sep. 05, 2011
8,9
10
8,9
10
OE# wave in Timing chart
Input signal state in power-on
PEDR48V256A-06 Oct. 17, 2011 1-12 1-12
Changed corporate name and logo to LAPIS
Semiconductor.
PEDR48V256A-06
MR48V256A
12/12
NOTES
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MR48V256ATAZBARL

Mfr. #:
Manufacturer:
Description:
IC FRAM 256K PARALLEL 28TSOP I
Lifecycle:
New from this manufacturer.
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