70V3399S166BC Datasheet 70V3319S166PRFG, 70V3319S166BF, 70V3399S133BFGI8 | P1-P3

OCTOBER 2014

DSC 5623/10

1



Functional Block Diagram

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

◆

Selectable Pipelined or Flow-Through output mode

– Due to limited pin count PL/

FT

option is not supported

on the 128-pin TQFP package. Device is pipelined

outputs only on each port.

◆

Counter enable and repeat features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (6Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

Dual Cycle Deselect (DCD) for Pipelined Output mode

◆

LVTTL- compatible, single 3.3V (±150mV) power supply

for core

◆

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

◆

Available in a 128-pin Thin Quad Flatpack, 208-pin fine

pitch Ball Grid Array, and 256-pin Ball

Grid Array

◆

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package

◆

Green parts available, see ordering information

HIGH-SPEED 3.3V

256/128K x 18

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V3319/99S

Dout0-8_L

B

W

0

L

B

W

1

L

Din_L

OE

L

UB

L

LB

L

R/W

L

CE

0L

CE

1L

ab

FT/PIPE

L 0/1

1b 0b 1a 0a

1

0

1/0

0b 1b0a 1a

ab

FT/PIPE

L

1/0

R EPEAT

R

A

17R

(1)

A

0R

CNTEN

R

ADS

R

Dout0-8_R

Dout9-17_R

I/O

0R

-I/O

17R

Din_R

ADDR_R

OE

R

UB

R

LB

R

R/W

R

CE

0R

CE

1R

FT/PIPE

R

CLK

R

,

Counter/

Address

Reg.

B

W

1

R

B

W

0

R

FT/PIPE

R

Counter/

Address

Reg.

CNTEN

L

ADS

L

REPEAT

L

Dout9-17_L

I/O

0L

-I/O

17L

A

17 L

(1)

A

0L

ADDR_L

5623 tbl 01

256K x 18

MEMORY

ARRAY

CLK

L

,

JTAG

TCK

TRST

TMS

TDO

TDI

ba

0/1

0b 1b

0a 1a

1

0

1/0

1b 0b 1a 0a

ab

1/0

NOTE:

1. A

17 is a NC for IDT70V3399.

6.42

IDT70V3319/99S

High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

2

Description:

The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to

allow simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70V3319/99 has been optimized for applications having unidirectional

or bidirectional data flow in bursts. An automatic power down feature,

controlled by CE

0 and CE1, permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70V3319/99 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power supply

for the core of the device (V

DD) remains at 3.3V.

Pin Configuration

(1,2,3,4,5)

NOTES:

1. A

17 is a NC for IDT70V3399.

2. All V

DD pins must be connected to 3.3V power supply.

3. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

4. All V

SS pins must be connected to ground supply.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

1716

15

1412 13

10

9876543

21

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

I/O

9L

NC V

SS

TDO

A

2L

A

4L

CLK

L

A

8L

A

12L

A

16L

NC OPT

L

NC

V

SS

NC

TDI

A

1L

A

5L

A

9L

A

13L

A

17L

(1 )

V

DDQL

I/O

9R

V

DDQR

PIPE/

FT

L

A

3L

A

6L

NC

A

10L

A

14L

NC

NC V

SS

I/O

10L

NC

I/O

11L

NC

V

DDQR

I/O

10R

NC

I/O

11R

NC

V

SS

V

DD

NC I/O

12L

V

DD

V

SS

V

SS

NC

V

SS

I/O

12R

REPEAT

R

NC I/O

14L

V

DDQR

V

DDQL

I/O

15R

NC

V

SS

NCNC

A

15L

A

11L

A

7L

A

0L

NC

I/O

7L

NC

I/O

6L

I/O

8R

UB

L

NC

I/O

8L

V

DDQL

CE

0L

CE

1L

LB

L

REPEAT

L

OE

L

I/O

0L

I/O

2L

I/O

1R

ADS

R

R/W

R

NC

I/O

16R

I/O

15L

TRST

A

13R

A

12R

NC

V

DD

CLK

R

I/O

0R

NC

A

17R

(1)

TCK

TMS

A

5R

A

9R

CE

0R

CE

1R

V

DD

V

SS

NC

A

16R

NC

A

14R

A

10R

UB

R

V

SS

V

DDQL

I/O

1L

I/O

2R

NC

NC A

15R

A

11R

A

7R

LB

R

OE

R

V

SS

NC

V

DDQL

OPT

R

NC

70V3319/99BF

BF-208

(6)

208-Pin fpBGA

Top View

(7)

5623 drw 02c

I/O

14R

V

DDQL

V

SS

V

DDQR

NC

I/O

7R

NC

R/W

L

NC

ADS

L

V

DDQL

I/O

13R

CNTEN

L

V

SS

I/O

13L

V

SS

I/O

16L

V

DDQR

V

SS

I/O

17R

I/O

17L

V

DDQL

V

SS

PIPE/

FT

R

A

8R

CNTEN

R

A

6R

A

3R

A

1R

A

2R

A

0R

I/O

3L

I/O

4L

A

4R

V

DD

V

SS

V

SS

V

SS

V

DDQR

V

DDQL

V

SS

V

DDQR

V

SS

I/O

3R

I/O

4R

V

SS

V

DDQR

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

5R

I/O

5L

V

DDQR

I/O

6R

V

SS

V

SS

V

DDQL

V

DD

V

SS

V

DDQR

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

08/01/02

6.42

IDT70V3319/99S

High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

3

Pin Configuration

(1,2,3,4,5)

(con't.)

NOTES:

1. A

17 is a NC for IDT70V3399.

2. All V

DD pins must be connected to 3.3V power supply.

3. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

4. All V

SS pins must be connected to ground supply.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

70V3319/99BC

BC-256

(6)

256-Pin BGA

Top View

(7)

E16

I/O

7R

D16

I/O

8R

C16

I/O

8L

B16

NC

A16

NC

A15

NC

B15

NC

C15

NC

D15

NC

E15

I/O

7L

E14

NC

D14

NC

D13

V

DD

C12

A

6L

C14

OPT

L

B14

V

DD

A14

A

0L

A12

A

5L

B12

A

4L

C11

ADS

L

D12

V

DDQR

D11

V

DDQR

C10

CLK

L

B11

RE PEAT

L

A11

CNTEN

L

D8

V

DDQR

C8

NC

A9

CE

1L

D9

V

DDQL

C9

LB

L

B9

CE

0L

D10

V

DDQL

C7

A

7L

B8

UB

L

A8

NC

B13

A

1L

A13

A

2L

A10

OE

L

D7

V

DDQR

B7

A

9L

A7

A

8L

B6

A

12L

C6

A

10L

D6

V

DDQL

A5

A

14L

B5

A

15L

C5

A

13L

D5

V

DDQL

A4

B4

NC

C4

A

16L

D4

PIPE/

FT

L

A3

NC

B3

TDO

C3

V

SS

D3

NC

D2

I/O

9R

C2

I/O

9L

B2

NC

A2

TDI

A1

NC

B1

NC

C1

NC

D1

NC

E1

I/O

10R

E2

I/O

10L

E3

NC

E4

V

DDQL

F1

I/O

11L

F2

NC

F4

V

DDQL

G1

NC

G2

NC

G3

I/O

12L

G4

V

DDQR

H1

NC

H2

I/O

12R

H3

NC

H4

V

DDQR

J1

I/O

13L

J2

I/O

14R

J3

I/O

13R

J4

V

DDQL

K1

NC

K2

NC

K3

I/O

14L

K4

V

DDQL

L1

I/O

15L

L2

NC

L3

I/O

15R

L4

V

DDQR

M1

I/O

16R

M2

I/O

16L

M3

NC

M4

V

DDQR

N1

NC

N2

I/O

17R

N3

NC

N4

PIPE/

FT

R

P1

NC

P2

I/O

17L

P3

TMS

P4

A

16R

R1

NC

R2

NC

R3

TRST

R4

NC

T1

NC

T2

TCK

T3

NC

T4

A

17R

(1)

P5

A

13R

R5

A

15R

P12

A

6R

P8

NC

P9

LB

R

R8

UB

R

T8

NC

P10

CLK

R

T11

CNTEN

R

P11

ADS

R

R12

A

4R

T12

A

5R

P13

A

3R

P7

A

7R

R13

A

1R

T13

A

2R

R6

A

12R

T5

A

14R

T14

A

0R

R14

OPT

R

P14

NC

P15

NC

R15

NC

T15

NC

T16

NC

R16

NC

P16

I/O

0L

N16

NC

N15

I/O

0R

N14

NC

M16

NC

M15

I/O

1L

M14

I/O

1R

L16

I/O

2R

L15

NC

L14

I/O

2L

K16

I/O

3L

K15

NC

K14

NC

J16

I/O

4L

J15

I/O

3R

J14

I/O

4R

H16

I/O

5R

H15

NC

H14

NC

G16

NC

G15

NC

G14

I/O

5L

F16

I/O

6L

F14

I/O

6R

F15

NC

R9

CE

0R

R11

REPEAT

R

T6

A

11R

T9

CE

1R

A6

A

11L

B10

R/W

L

C13

A

3L

P6

A

10R

R10

R/W

R

R7

A

9R

T10

OE

R

T7

A

8R

,

E5

V

DD

E6

V

DD

E7

V

SS

E8

V

SS

E9

V

SS

E10

V

SS

E11

V

DD

E12

V

DD

E13

V

DDQR

F5

V

DD

F6

V

SS

F8

V

SS

F9

V

SS

F10

V

SS

F12

V

DD

F13

V

DDQR

G5

V

SS

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

SS

G12

V

SS

G13

V

DDQL

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

SS

H13

V

DDQL

J5

V

SS

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

V

SS

J13

V

DDQR

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

L5

V

DD

L6

V

SS

L7

V

SS

L8

V

SS

M5

V

DD

M6

V

DD

M7

V

SS

M8

V

SS

N5

V

DDQR

N6

V

DDQR

N7

V

DDQL

N8

V

DDQL

K9

V

SS

K10

V

SS

K11

V

SS

K12

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DD

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DD

N9

V

DDQR

N10

V

DDQR

N11

V

DDQL

N12

V

DDQL

K13

V

DDQR

L13

V

DDQL

M13

V

DDQL

N13

V

DD

F7

V

SS

F11

V

SS

5623 drw 02d

,

F3

I/O

11R

08/01/02

A

17L

(1)

70V3399S166BC

70V3399S166BC

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