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70V3399S166BC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configuration
(1,2,3,4,5,8,9)
(con't.)
NOTES:
1. A
17 is a NC for IDT70V3399.
2. All V
DD pins must be connected to 3.3V power supply.
3. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
4. All V
SS pins must be connected to ground supply.
5. Package body is approximately 14mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. PIPE/FT option in PK-128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port.
9. Due to the limited pin count, JTAG is not supported in the PK-128 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
A
14L
A
15L
A
16L
A
17L
(1)
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
A
17R
(1)
A
16R
A
15R
A
14R
A
1R
A
0R
OPT
R
IO
0L
IO
0R
V
DDQR
V
SS
IO
1L
IO
1R
V
DDQL
V
SS
IO
2L
IO
2R
IO
3L
IO
3R
IO
4L
IO
4R
V
SS
V
SS
V
DD
V
DD
IO
5L
IO
5R
V
DDQR
V
SS
IO
7R
IO
7L
V
DDQL
V
SS
V
SS
IO
8R
IO
8L
V
SS
OPT
L
A
0L
A
1L
IO
6R
IO
6L
70V3319/99PRF
PK-128
(6)
128-Pin TQFP
Top View
(7)
5623 drw 02a
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
U
B
L
L
B
L
C
E
1
L
C
E
0
L
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
L
O
E
L
R
/
W
L
A
D
S
L
C
N
T
E
N
L
R
E
P
E
A
T
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
U
B
R
L
B
R
C
E
1
R
C
E
0
R
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
R
O
E
R
R
/
W
R
A
D
S
R
C
N
T
E
N
R
R
E
P
E
A
T
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
.
08/06/02
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
5
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
(6 )
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
17L
(1 )
A
0R
- A
17R
(1 )
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
PIPE/FT
L
(5)
PIPE/FT
R
(5 )
Pipeline/Flow-Through
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
REP EAT
L
REPEAT
R
Counter Repeat
(4 )
UB
L
UB
R
Upper Byte Enable (I/O
9
-I/O
17
)
(6 )
LB
L
LB
R
Lower Byte Enable (I/O
0
-I/O
8
)
(6 )
V
DDQ L
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(2 )
OPT
L
OPT
R
Option for selecting V
DDQX
(2,3)
V
DD
Power (3.3V)
(2)
V
SS
Ground (0V)
TDI Test Data Input
TDO Test Data Output
TCK Test Logic Clock (10MHz)
TMS Test Mode Select
TRS T
Reset (Initialize TAP Controller)
5623 tbl 01
1. A17 is a NC for IDT70V3399.
2. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEAT
X is asserted, the counter will reset to the last valid address loaded
via ADS
X.
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH, i.e., the
signals take two cycles to deselect.
NOTES:
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
6
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
CLK
CE
0
CE
1
UB LB
R/W
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X
↑
HXXXX High-Z High-ZDeselected–Power Down
X
↑
X L X X X High-Z High-Z Deselected–Power Down
X
↑
L H H H X High-Z High-Z Both Bytes Deselected
X
↑
LHHLL High-Z D
IN
Write to Lower Byte Only
X
↑
LHLHL D
IN
High-Z Write to Upper Byte Only
X
↑
LHLLL D
IN
D
IN
Write to Both Bytes
L
↑
LHHLH High-Z D
OUT
Read Lower Byte Only
L
↑
LHLHH D
OUT
High-Z Read Upper Byte Only
L
↑
LHLLH D
OUT
D
OUT
Read Both Bytes
H
↑
L H L L X High-Z High-Z Outputs Disabled
5623 tbl 02
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
0, CE1 and UB, LB.
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB, LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
External
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS CN T EN REPEAT
(6 )
I/O
(3 )
MODE
XXAn
↑
XX L
(4 )
D
I/O
(0) Counter Reset to last valid ADS load
An X An
↑
L
(4 )
XHD
I/O
(n) External Address Used
An Ap Ap
↑
HH H D
I/O
(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
↑
H L
(5 )
HD
I/O
(p+1) Counter Enabled—Internal Address generation
5623 tbl 03
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

70V3399S166BC

Mfr. #:
Buy 70V3399S166BC
Manufacturer:
IDT
Description:
SRAM 128Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
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