ADADC80
Rev. E | Page 12 of 16
Other Ranges
Coding relationships and calibration points for 0 V to +5 V,
−2.5 V to +2.5 V, and −5 V to +5 V ranges can be found by
halving the corresponding code equivalents listed for the 0 V to
+10 V and −10 V to +10 V ranges, respectively.
Zero and full-scale calibration can be accomplished to a
precision of approximately ±1/4 LSB using the static adjustment
procedure described previously. By summing a small sine- or
triangular-wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end points) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented
in A/D Conversion Notes, D. Sheingold, Analog Devices, Inc.,
1977, Part II, Chapter 3.
GROUNDING
Many data-acquisition components have two or more ground
pins that are not connected together within the device. These
grounds are usually referred to as the logic power return, analog
common (analog power return), and analog signal ground.
These grounds must be tied together at one point, usually at the
system power-supply ground. Ideally, a single solid ground is
desirable. However, because current flows through the ground
wires and etch stripes of the circuit cards, and because these
paths have resistance and inductance, hundreds of millivolts can
be generated between the system ground point and the ground
pin of the ADADC80. Therefore, separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point, and the two
device grounds should be tied together. In this way, supply
currents and logic gate return currents are not summed into the
same return path as analog signals, where they would cause
measurement errors.
Each of the ADADC80 supply terminals should be capacitively
decoupled as close to the ADADC80 as possible. A large value
capacitor, such as 1 μF in parallel with a 0.1 μF capacitor, is
usually sufficient. Analog supplies are bypassed to the analog
power return pin, and the logic supply is bypassed to the logic
power return pin.
17 15 25 10 9
ADADC80
AD583
SAMPLE AND
HOLD
*ANALOG
GROUND
AD521
INST. AMP
OUTPUT
REFERENCE
0.01
µF
0.01
µF
0.01
µF
0.01
µF
0.01
µF
0.01
µF
0.01
µF
DIG
COM
5VC–15VC+15V
ANALOG
PS
DIGITAL
PS
*IF INDEPENDENT, OTHERWISE RETURN
AMPLIFIER REFERENCE TO MECCA AT
ANALOG P.S. COMMON.
01202-015
15V OR
12V
–15V OR
–12V
ANALOG
GND
DIGITAL
GND
5V
DIGITAL
SUPPLY
DIGITAL
GROUND
Figure 15. Basic Grounding Practice
