74ALVCH162374PAG

INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
(1)
Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 V
V
CC = 2.3V IOH = – 4mA 1.9
IOH = – 6mA 1.7
V
CC = 2.7V IOH = – 4mA 2.2
IOH = – 8mA 2
VCC = 3V IOH = – 6mA 2.4
IOH = – 12mA 2
V
OL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA 0.2 V
V
CC = 2.3V IOL = 4mA 0.4
IOL = 6mA 0.55
VCC = 2.7V IOL = 4mA 0.4
IOL = 8mA 0.6
VCC = 3V IOL = 6mA 0.55
IOL = 12mA 0.8
SWITCHING CHARACTERISTICS
(1)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 28 31 pF
CPD Power Dissipation Capacitance Outputs disabled 10 11
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMAX 150 150 150 MHz
tPLH Propagation Delay 1 5.4 5.4 1 4.6 ns
tPHL xCLK to xQx
t
PZH Output Enable Time 1 6.5 6.4 1 5.2 ns
tPZL xOE to xQx
t
PHZ Output Disable Time 1 5.6 5 1.2 4.5 ns
tPLZ xOE to xQx
tSU Setup Time, data before CLK 2.1 2.2 1.9 ns
tH Hold Time, data after CLK 0.6 0.5 0.5 ns
tW Pulse Duration, LE HIGH or LOW 3.3 3.3 3.3 ns
tSK(O) Output Skew
(2)
———500 ps
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500Ω
500Ω
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DIS-
ABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC
(1)
= 3.3V±0.3V VCC
(1)
= 2.7V VCC
(2)
= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT 1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
C
L 50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low V
LOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PAG
162
74
Thin Shrink Small Outline Package - Green
16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs
– 40°C to +85°C
XXX
Family
Bus-Hold
374
Bus-Hold
Double-Density with Resistors, ±12mA
H
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com

74ALVCH162374PAG

Mfr. #:
Manufacturer:
IDT
Description:
Flip Flops 16BIT EDGE TRIG D TYPE
Lifecycle:
New from this manufacturer.
Delivery:
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