1©2016 Integrated Device Technology, Inc Revision A January 15, 2016
General Description
The 840001I-34 is a two output LVCMOS/LVTTL Synthesizer. One
output is the LVCMOS/LVTTL main synthesized clock output (Q)
and one output is a three-state LVCMOS/LVTTL reference clock
(REF_OUT) output at the frequency of the crystal oscillator. The
device can accept crystals from 15.3125MHz to 42.67MHz and
can synthesize outputs from 81.67MHz to 213.33MHz. The
840001I-34 is packaged in a 3mm x 3mm 16-pin VFQFN, making
it ideal for use on space constrained boards.
Features
Two LVCMOS/LVTTL outputs, 22 typical output impedance
One main clock output (Q)
One three-state reference clock output (REF_OUT)
Crystal oscillator interface can accept crystals from
15.3125MHz to 42.67MHz, 18pF parallel resonant crystal
Q output frequency range: 81.67MHz to 213.33MHz
RMS phase jitter @106.25, (637kHz – 10MHz): 0.38ps (typical)
VCO range: 490MHz to 640MHz
Full 3.3V and 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Common Application Configuration Table
Block Diagram
Inputs
Output Frequency
(MHz) ApplicationCrystal (MHz) M Divider VCO (MHz) N Divider
40 15 600 6 100 (default)
Serial Attached (SCSI),
PCI Express, Processor Clock
26.5625 24 637.5 6 106.25 Fibre Channel
40 15 600 4 150 Serial ATA (SATA), Processor Clock
26.5625 24 637.5 3 212.5 Fibre Channel 2
25 25 625 5 125 Ethernet
25 25 625 4 156.25 10 Gigabit Ethernet
22.5 25 562.5 3 187.5 12 Gigabit Ethernet
19.44 32 622.08 4 155.52 SONET
OSC
Phase
Detector
VCO
490MHz - 640MHz
N-Div
00 = ÷3
01 = ÷4
10 = ÷5
11 = ÷6
(default)
M-Div
11 = ÷15
(default)
10 = ÷24
01 = ÷25
00 = ÷32
REF_OUT
Q
OE
M1
M0
N1
XTAL_IN
XTAL_OUT
(Pullup)
(Pullup)
(Pullup)
(Pullup)
(Pullup)
N0
5 6 7 8
16 15 14 13
1
2
3
4
12
11
10
9
OE
XTAL_IN
XTAL_OUT
M0
Q
V
DDO
GND
V
DD
M1
nc
N0
N1
nc
nc
REF_OUT
V
DDA
Pin Assignment
840001-34
16 Lead VFQFN
3mm x 3mm x 0.925 package body
K Package
Top View
Femtoclocks™ Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
840001I-34
Data Sheet
2©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 OE Input Pullup
Output enable pin. When HIGH, REF_OUT output is enabled. When LOW,
forces REF_OUT to Hi-Z state. See Table 3A. LVCMOS/LVTTL interface levels.
2,
3
XTAL_IN,
XTAL_OUT
Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
4, 5 M0, M1 Input Pullup M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B.
6, 14, 15 nc Unused No connect.
7, 8 No, N1 Input Pullup
Determines output divider value as defined in Table 3C.
LVCMOS/LVTTL interface levels.
9V
DD
Power Core supply pin.
10 GND Power Power supply ground.
11 V
DDO
Power Output supply pin.
12 Q Output
Single-ended clock output. 22 typical output impedance.
LVCMOS/LVTTL interface levels.
13 REF_OUT Output
Single-ended three-state reference clock output. 22 typical output impedance.
LVCMOS/LVTTL interface levels.
16 V
DDA
Power Analog supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
V
DD,
V
DDO
= 3.465V 8 pF
V
DD,
V
DDO
= 2.625V 6 pF
R
PULLUP
Input Pullup Resistor 51 k
R
OUT
Output Impedance
V
DD,
V
DDO
= 3.3V±5% 14 22 30
V
DD,
V
DDO
= 2.5V±5% 16 26 36
3©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
Table 3A. Control Input Function Table
Table 3B. M Divider Function Table
Table 3C. N Divider Function Table
Control Input Output
OE REF_OUT
0 Hi-Z
1 Active (default)
Control Inputs
Feedback Divider RatioM1 M0
00 ÷32
01 ÷25
10 ÷24
1 1 ÷15 (default)
Control Inputs
Output Divider RatioN1 N0
00 ÷3
01 ÷4
10 ÷5
1 1 ÷6 (default)

840001AKI-34LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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