9©2016 Integrated Device Technology, Inc Revision A January 15, 2016
840001I-34 Data Sheet
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. The ICS40001I-34 provides separate power supplies to
isolate any high switching noise from the outputs to the internal
PLL. V
DD,
V
DDA,
and V
DDO
should be individually connected to the
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic
V
DD
pin and also shows that V
DDA
requires that an additional 10
resistor along with a 10F bypass capacitor be connected to the
V
DDA
pin.
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1k
resistor can be used.
Outputs:
LVCMOS Output
All unused LVCMOS output can be left floating. There should be
no trace attached.
Crystal Input Interface
The 840001I-34 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
Figure 2. Crystal Input Interface
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
33pF
C2
33pF
