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CY7C199CL-15ZXC

P1-P3P4-P6P7-P9P10-P12P13-P13
256K (32K x 8) Static RAM
CY7C199C
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05408 Rev. *B Revised November 05, 2004
Features
• Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL–compatible Inputs and Outputs
• Available in 28 DIP, 28 SOJ, and 28 TSOP I packages
• Also available in Lead-Free 28 DIP
• 2.0V Data Retention
• Low CMOS standby power
• Automated Power-down when deselected
General Description
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C199C is available in 28 DIP, 28 SOJ, and 28 TSOP I
package(s).
Product Portfolio
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Row Decoder
RAM Array
Column Decoder
Input Buffer
Sense Amps
A
X
Power
Down
Circuit
I/Ox
OE
WE
CE
X
Logic Block Diagram
12 ns 15 ns 20 ns 25 ns Unit
Maximum Access Time 12 15 20 25 ns
Maximum Operating Current 85 80 75 75 mA
Maximum CMOS Standby Current
(low power)
500 500 500 500 µA
CY7C199C
Document #: 38-05408 Rev. *B Page 2 of 13
Pin Layout and Specifications
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
OE
A
1
A
2
A
3
A
4
WE
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 DIP (6.9 x 35.6 x 3.5 mm) – P21
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 TSOP I (8 x 13.4 mm) – Z28
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
OE
A
1
A
2
A
3
A
4
WE
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 SOJ – V21
CY7C199C
Document #: 38-05408 Rev. *B Page 3 of 13
Truth Table
Pin Description
Pin Type Description DIP SOJ TSOP I
A
X
Input Address Inputs 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 21, 23,
24, 25, 26
1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 21, 23,
24, 25, 26
2, 3, 4, 5, 8, 9,
10, 11, 12, 13,
14, 15, 16, 17,
28
CE Control Chip Enable 20 20 27
I/O
X
Input or
Output
Data Input/Outputs 11, 12, 13, 15,
16, 17, 18, 19
11, 12, 13, 15,
16, 17, 18, 19
18, 19, 20, 22,
23, 24, 25, 26
OE Control Output Enable 22 22 1
V
CC
Supply Power (5.0V) 28 28 7
V
SS
Supply Ground 14 14 21
WE Control Write Enable 27 27 6
P1-P3P4-P6P7-P9P10-P12P13-P13

CY7C199CL-15ZXC

Mfr. #:
Buy CY7C199CL-15ZXC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 256K PARALLEL 28TSOP I
Lifecycle:
New from this manufacturer.
Delivery:
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