CY7C199C
Document #: 38-05408 Rev. *B Page 6 of 13
Thermal Resistance
[4]
Parameter Description Conditions TSOP I SOJ DIP Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a
3 × 4.5 square inch,
two–layer printed
circuit board
88.6 79 TBD °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
21.94 41.42 TBD
AC Electrical Characteristics
[5, 6, 7]
Parameter Description
12 ns 15 ns 20 ns 25 ns
UnitMin Max Min Max Min Max Min Max
t
RC
Read Cycle Time 12 – 15 – 20 – 25 – ns
t
AA
Address to Data Valid – 12 – 15 – 20 – 25 ns
t
OHA
Data Hold from Address
Change
3 – 3 – 3 – 3 – ns
t
ACE
CE to Data Valid – 12 – 15 – 20 – 25 ns
t
DOE
OE to Data Valid – 5 – 7 – 9 – 9 ns
t
LZOE
OE to Low Z 0 – 0 – 0 – 0 – ns
t
HZOE
OE to High Z – 5 – 7 – 9 – 9 ns
t
LZCE
CE to Low Z 3 – 3 – 3 – 3 – ns
t
HZCE
CE to High Z – 5 – 7 – 9 – 9 ns
t
PU
CE to Power-up 0 – 0 – 0 – 0 – ns
t
PD
CE to Power-down – 12 – 15 – 20 – 20 ns
t
WC
Write Cycle Time 12 – 15 – 20 – 25 – ns
t
SCE
CE to Write End 9 – 10 – 15 – 15 – ns
t
AW
Address Set-up to Write End 9 – 10 – 15 – 15 – ns
t
HA
Address Hold from Write End 0 – 0 – 0 – 0 – ns
t
SA
Address Set-up to Write Start 0 – 0 – 0 – 0 – ns
t
PWE
WE Pulse Width 8 – 9 – 15 – 15 – ns
t
SD
Data Set-up to Write End 8 – 9 – 10 – 10 – ns
t
HD
Data Hold from Write End 0 – 0 – 0 – 0 – ns
t
HZWE
WE LOW to High Z – 7 – 7 – 10 – 10 ns
t
LZWE
WE HIGH to Low Z 3 – 3 – 3 – 3 – ns
Data Retention Characteristics
[8]
Parameter Description Condition
ALL
UnitMin Max
V
DR
V
CC
for Data Retention 2.0 – V
I
CCDR
Data Retention Current V
CC
= V
DR
=2.0V, CE ≥ V
CC
– 0.3V, V
IN
≥ V
CC
– 0.3V or V
IN
≤ 0.3V
– 150 mA
t
CDR
Chip Deselect to Data
Retention Time
0 – ns
t
R
Operation Recovery Time 200 – µs
Notes:
4. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
8. L-version only.
