ADT75 Data Sheet
Rev. B | Page 12 of 24
ONE-SHOT MODE
Setting Bit D5 of the configuration register enables the one-shot
mode. When this mode is enabled, the ADT75 goes immediately
into shutdown mode and the current consumption is reduced to
typically 3 µA when V
DD
is 3.3 V and 5.5 µA when V
DD
is 5 V. A
one-shot temperature measurement is initiated when Address 0x04
is written to the address pointer register, which is writing to the
one-shot register. The ADT75 powers up, does a temperature
conversion, and powers down again.
Wait for a minimum of 60 ms after writing to the one-shot register
before reading back the temperature. This time ensures the ADT75
has time to power up and do a conversion. Reading back from the
one-shot register, Address 0x04, gives the resultant temperature
conversion. Reading from the temperature value register also
gives the same temperature value.
When either of the overtemperature detection modes is selected, a
write to the one-shot register, Address 0x04, causes the OS/ALERT
pin to go active if the temperature exceeds the overtemperature
limits. Refer to Figure 12 for more information on one-shot
OS/ALERT pin operation.
Note: In the interrupt mode, a read from any register resets the
OS/ALERT pin after it is activated by a write to the one-shot
register. In the comparator mode, once the temperature drops
below the value in the T
HYST
register, a write to the one-shot
register resets the OS/ALERT pin.
The one-shot mode is useful when one of the circuit design
priorities is to reduce power consumption.
TEMPERATURE
82°C
81°C
80°C
79°C
78°C
77°C
76°C
75°C
74°C
73°C
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = ACTIVE LOW
OS/ALERT PIN
(INTERRUPT MODE)
POLARITY = ACTIVE LOW
OS/ALERT PIN
(INTERRUPT MODE)
POLARITY = ACTIVE HIGH
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = ACTIVE HIGH
T
OS
T
HYST
TIME
READ
1
READ
1
READ
1
WRITE TO
0x04 REG.
2
WRITE TO
0x04 REG.
2
WRITE TO
0x04 REG.
2
05326-022
1
READ FROM ANY REGISTER.
2
THERE IS A 60ms DELAY BETWEEN WRITING TO THE
ONE-SHOT REGISTER AND THE OS/ALERT PIN GOING
ACTIVE. THIS IS DUE TO THE CONVERSION TIME.
Figure 12. One-Shot OS/ALERT Pin Operation
FAULT QUEUE
Bit D3 and Bit D4 of the configuration register are used to set
up a fault queue. Up to six faults are provided to prevent false
tripping of the OS/ALERT pin when the ADT75 is used in a
noisy temperature environment. The number of faults set in the
queue must occur consecutively to set the OS/ALERT output.