ADT75ARMZ Datasheet ADT75ARMZ, ADT75BRMZ, ADT75BRMZ-REEL7 | P19-P21

ADT75 Data Sheet

Rev. B | Page 18 of 24

05326-015

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

ACK. BY

ADT75

ACK. BY

ADT75

ACK. BY

ADT75

STOP BY

MASTER

FRAME 4

DATA BYTE

SCL

SDA

START BY

MASTER

1 0 0 1 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

D7 D6 D5 D4 D3 D2 D1 D0

R/W

191

ACK. BY

ADT75

FRAME 3

DATA BYTE

SDA (CONTINUED)

SCL (CONTINUED)

D15 D14 D13 D12 D11 D10 D9 D8

Figure 16. Writing to the Address Pointer Register Followed by Two Bytes of Data to Either T

HYST

or T

Registers

SCL

SDA

1 0 0 1 A2A1 A0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS

BYTE

FRAME 2

DATA BYTE FROM CONFIGURATION

STOP BY

MASTER

ACK. BY

ADT75

NO ACK. BY

MASTER

R/W D7 D6 D5 D4 D3 D2 D1 D0

05326-016

Figure 17. Reading Back Data from the Configuration Register

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MSB DATA BYTE FROM TEMPERATURE

VALUE REGISTER

ACK. BY

ADT75

ACK. BY

MASTER

SCL

SDA

START BY

MASTER

1 0 0 1 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8

R/W

191

05326-017

NO ACK. BY

MASTER

STOP BY

MASTER

FRAME 3

LSB DATA BYTE FROM TEMPERATURE

VALUE REGISTER

SDA (CONTINUED)

SCL (CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 18. Reading Back Data from the Temperature Value Register

READING DATA

Reading data from the ADT75 is done in a one data byte operation

for the configuration register and a two data byte operation for

the temperature value register, T

HYST

setpoint

is shown in Figure 17. Reading back the contents of the temperature

value register is shown in Figure 18. Reading back from any register

first requires a single-byte write operation to the address pointer

to be read from. To read from another register, execute another

write to the address pointer register to set up the relevant register

address. Thus, block reads are not possible, that is, there is no I

auto-increment. If the address pointer register has previously been

set up with the address of the register that is going to receive a

read command then there is no need to repeat a write operation

to set up the register address again.

Data Sheet ADT75

Rev. B | Page 19 of 24

OS/ALERT OUTPUT OVERTEMPERATURE MODES

The ADT75 has two overtemperature modes, comparator mode

and interrupt mode. The OS/ALERT pin defaults on power up

as an OS pin; the comparator mode is the default power up

overtemperature mode. The OS/ALERT output pin becomes

active when the temperature measured exceeds the temperature

limit stored in the T

setpoint register. How this pin reacts after

this event depends on the overtemperature mode selected.

Comparator Mode

In the comparator mode, the OS/ALERT pin returns to its

inactive status when the temperature measured drops below the

limit stored in the T

HYST

setpoint register. Putting the ADT75

into shutdown mode does not reset the OS/ALERT state in

comparator mode.

Interrupt Mode

In the interrupt mode, the OS/ALERT pin goes inactive when

any ADT75 register is read. The OS/ALERT pin can only return

to active status if the temperature measured is below the limit

stored in the T

HYST

setpoint register. Once the OS/ALERT pin is

reset, it goes active again only when the temperature has gone

above the T

limit. The OS/ALERT pin can also be reset by a

SMBus alert response address (ARA) when this pin has been

selected as a SMBus alert pin. More information is given in the

SMBUS Alert section.

Figure 19 illustrates the comparator and interrupt modes with

both pin polarity settings. Placing the ADT75 into shutdown

mode resets the OS/ALERT pin in the interrupt mode.

TEMPERATURE

82°C

81°C

80°C

79°C

78°C

77°C

76°C

75°C

74°C

73°C

OS/ALERT PIN

(COMPARATOR MODE)

POLARITY = ACTIVE LOW

OS/ALERT PIN

(INTERRUPT MODE)

POLARITY = ACTIVE LOW

OS/ALERT PIN

(INTERRUPT MODE)

POLARITY = ACTIVE HIGH

OS/ALERT PIN

(COMPARATOR MODE)

POLARITY = ACTIVE HIGH

HYST

TIME

READ

READ READ

05326-018

Figure 19. OS/ALERT Output Temperature Response Diagram

ADT75 Data Sheet

Rev. B | Page 20 of 24

SMBus ALERT

The OS/ALERT pin can behave as a SMBus alert pin when the

SMBus alert function is enabled by setting Bit D7 in the

configuration register. The interrupt mode must also be selected

(Bit D1 in the configuration register). The OS/ALERT pin is an

open-drain output and requires a pull-up to V

. Several SMBus

alert outputs can be wire-AND’ed together, so that the common

line goes low if one or more of the SMBus alert outputs goes

low. The polarity of the OS/ALERT pin must be set for active

low for a number of outputs to be wire-AND’ed together.

The OS/ALERT output can operate as a

SMBALERT

function.

Slave devices on the SMBus normally cannot signal to the master

that they want to talk, but the

SMBALERT

function allows them to

do so.

SMBALERT

is used in conjunction with the SMBus general

call address.

One or more SMBus alert outputs can be connected to a common

SMBALERT

line connected to the master. When the

SMBALERT

line is pulled low by one of the devices, the following procedure

occurs as shown in

Figure 20.

MASTER

RECEIVES

SMBALERT

START

ALERT RESPONSE

ADDRESS

RD ACK DEVICE ADDRESS

MASTER SENDS

ARA AND READ

COMMAND

DEVICE SENDS

ITS ADDRESS

ACK

STOP

05326-019

Figure 20. ADT75 Responds to

SMBALERT

ARA

SMBALERT

is pulled low.

2. Master initiates a read operation and sends the SMBus alert

response address (ARA = 0001 100). This reserved SMBus/

C address must not be used as a specific device address.

3. The device whose SMBus alert output is low responds to the

SMBus alert response address and the master reads its device

address. As the device address is seven bits long, the ADT75’s

LSB is free to be used as an indicator as to which temperature

limit was exceeded. The LSB is high if the temperature is

greater than or equal to T

, and the LSB is low if the

temperature is less than T

HYST

. The address of the device

is now known and it can be interrogated in the usual way.

4. If more than one devices’ SMBus alert output is low, the one

with the lowest device address has priority, which is in

accordance with normal SMBus specifications.

Once the ADT75 has responded to the SMBus alert response

address, it resets its SMBus alert output. If the

SMBALERT

line

remains low, the master sends the ARA again. It continues to do

this until all devices whose

SMBALERT

outputs were low have

responded.

START

ALERT RESPONSE

ADDRESS

RD ACK

DEVICE

ADDRESS

MASTER SENDS

ARA AND READ

COMMAND

DEVICE SENDS

ITS ADDRESS

DEVICE ACK

ACK PEC

ACK

STOP

MASTER

ACK

MASTER

NACK

DEVICE SENDS

ITS PEC DATA

05326-020

MASTER

RECEIVES

SMBALERT

Figure 21. ADT75 Responds to

SMBALERT

ARA with

Packet Error Checking (PEC)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADT75ARMZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Board Mount Temperature Sensors 1 Deg C Accurate 12-Bit Digital

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ADT75ARMZ

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