AD7788/AD7789 Data Sheet
Rev. C | Page 14 of 20
ADC CIRCUIT INFORMATION
The AD7788/AD7789 are low power ADCs that incorporate a
Σ-Δ modulator and on-chip digital filtering intended for the
measurement of wide dynamic range, low frequency signals,
such as those in pressure transducers, weigh scales, and temper-
ature measurement applications. The device has one unbuffered
differential input. The device requires an external reference
voltage between 0.1 V and V
DD
. Figure 10 shows the basic
connections required to operate the device.
03539-006
IN+
10µF0.1µF
IN–
OUT–
POWER
SUPPLY
OUT+
REFIN(+)
CS
DOUT/RDY
SCLK
V
DD
GND
AIN(+)
AIN(–)
REFIN(–)
AD7788/
AD7789
MICROCONTROLLER
Figure 10. Basic Connection Diagram
The output rate of the AD7788/AD7789 (f
ADC
) is 16.6 Hz with
the settling time equal to 2 × t
ADC
(120.4 ms). Normal-mode
rejection is the major function of the digital filter. Simultaneous
50 Hz and 60 Hz rejection is optimized as notches are placed at
both 50 Hz and 60 Hz with this update rate (see Figure 6).
NOISE PERFORMANCE
Typically, the devices have an rms noise of 1.5 μV rms that
corresponds to a peak-to-peak resolution of 16 bits for the
AD7788 and 19 bits (equivalent to an effective resolution of
21.5 bits) for the AD7789. These numbers are for the bipolar
input range with a reference of 2.5 V. The noise was measured
with a differential input voltage of 0 V. The peak-to-peak
resolution figures represent the resolution for which there is no
code flicker within a six-sigma limit. The output noise comes
from two sources. The first is the electrical noise in the semi-
conductor devices (device noise) used in the implementation of
the modulator. The second is quantization noise, added when
the analog input is converted into the digital domain.
DIGITAL INTERFACE
As previously outlined, the AD7788/AD7789 programmable
functions are controlled using a set of on-chip registers. Data is
written to these registers via the serial interface and read access
to the on-chip registers is also provided by this interface. All
communications with the devices must start with a write to the
communications register. After power-on or reset, the devices
expect a write to the communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation, and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the devices begins with a
write operation to the communications register followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register followed by a read
operation from the selected register.
The AD7788/AD7789 serial interface consists of four signals:
CS
, DIN, SCLK, and DOUT/
RDY
. The DIN line is used to
transfer data into the on-chip registers and DOUT/
RDY
is used
for accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT/
RDY
) occur with respect to the SCLK signal. The
DOUT/
RDY
pin operates as a data ready signal also, the line
goes low when a new data-word is available in the output register.
It is reset high when a read operation from the data register is
complete. It also goes high prior to the data register update to
indicate when not to read from the device; this ensures that a
data read is not attempted while the register is being updated.
CS
is used to select a device. It can be used to decode the
AD7788/AD7789 in systems where several compo-nents are
connected to the serial bus.
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7788/AD7789 with
CS
being used to decode the devices.
Figure 3 shows the timing for a read operation from the output
shift register, while Figure 4 shows the timing for a write opera-
tion to the input shift register. In all modes except continuous
read mode, it is possible to read the same word from the data
register several times even though the DOUT/
RDY
line returns
high after the first read operation. However, care must be taken
to ensure that the read operations have been completed before
the next output update occurs. In continuous read mode, the
data register can be read only once.
The serial interface can operate in 3-wire mode by tying
CS
low.
In this case, the SCLK, DIN, and DOUT/
RDY
lines are used to
communicate with the AD7788/AD7789. The end of conversion
can be monitored using the
RDY
bit in the status register. This
scheme is suitable for interfacing to microcontrollers. If
CS
is
required as a decoding signal, it can be generated from a port
pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
The AD7788/AD7789 can operate with
CS
being used as a
frame synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by
CS
, because
CS
normally occurs after the falling edge of
SCLK in DSPs. The SCLK can continue to run between data
transfers, provided the timing numbers are obeyed.
