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AD7789BRM-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD7788/AD7789 Data Sheet
Rev. C | Page 4 of 20
AD7788
V
DD
= 2.5 V to 5.25 V (B grade); V
DD
= 2.7 V to 5.25 V (A grade); REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
AD7788A, AD7788B Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate 16.6 Hz nom
ADC CHANNEL
No Missing Codes
2
16 Bits min
Resolution 16 Bits p-p
Output Noise 1.5 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max B grade
ppm of FSR max
A grade
2
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error
3
±10 µV typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power Supply Rejection 90 dB min B grade
90 dB typ A grade
ANALOG INPUTS
Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) − REFIN(−)
Absolute AIN Voltage Limits
2
GND − 30 mV V min
V
DD
+ 30 mV V max
Analog Input Current
Input current varies with input
voltage
Average Input Current
2
±400 nA/V typ
Average Input Current Drift
pA/V/°C typ
Normal-Mode Rejection
2
At 50 Hz, 60 Hz 65 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
60 dB min A grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
Common-Mode Rejection AIN = 1 V
At DC 90 dB min B grade, 100 dB typ
90 dB typ A grade
At 50 Hz, 60 Hz
2
100 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
100 dB typ A grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
REFERENCE INPUT
REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range
2
0.1 V min
V
DD
V max
Absolute REFIN Voltage Limits
2
GND − 30 mV V min
DD
V max
Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal-Mode Rejection
2
At 50 Hz, 60 Hz 65 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
60 dB min A grade
Common-Mode Rejection AIN = 1 V
At DC 100 dB typ
At 50 Hz, 60 Hz 110 dB typ 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
1
Temperature range: B grade: −40°C to +105°C; A grade: −40°C to +85°C.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (V
DD
= 4 V).
Data Sheet AD7788/AD7789
Rev. C | Page 5 of 20
AD7788/AD7789
Table 3.
Parameter AD7788A, AD7788B/AD7789B Unit Test Conditions/Comments
LOGIC INPUTS
All Inputs Except SCLK
1
V
INL
, Input Low Voltage 0.8 V max V
DD
= 5 V
0.4 V max V
DD
= 3 V
V
INH
, Input High Voltage 2.0 V min V
DD
= 3 V or 5 V
SCLK Only (Schmitt-Triggered Input)
1
V
T
(+) 1.4/2 V min/V max V
DD
= 5 V
V
T
(−) 0.8/1.4 V min/V max V
DD
= 5 V
V
T
(+) − V
T
(−) 0.3/0.85 V min/V max V
DD
= 5 V
V
T
(+) 0.9/2 V min/V max V
DD
= 3 V
V
T
(−) 0.4/1.1 V min/V max V
DD
= 3 V
V
T
(+) − V
T
(−) 0.3/0.85 V min/V max V
DD
= 3 V
Input Currents ±1 µA max V
IN
= V
DD
Input Capacitance 10 pF typ All digital inputs
LOGIC OUTPUTS
V
OH
, Output High Voltage
1
V
DD
− 0.6 V min V
DD
= 3 V, I
SOURCE
= 100 µA
V
OL
, Output Low Voltage
1
0.4 V max V
DD
= 3 V, I
SINK
= 100 µA
V
OH
, Output High Voltage
1
4 V min V
DD
= 5 V, I
SOURCE
= 200 µA
V
OL
, Output Low Voltage
1
0.4 V max V
DD
= 5 V, I
SINK
= 1.6 mA
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary
POWER REQUIREMENTS
2
Power Supply Voltage
V
DD
− GND 2.5/5.25 V min/max AD7789, AD7788 B grade
2.7/5.25 V min/max AD7788 A grade
Power Supply Currents
I
DD
Current 75 µA max 65 µA typ, V
DD
= 3.6 V
80
µA max
73 µA typ, V
DD
= 5.25 V
I
DD
(Power-Down Mode) 1 µA max
1
Specification is not production tested but is supported by characterization data at initial product release.
2
Digital inputs equal to V
DD
or GND.
AD7788/AD7789 Data Sheet
Rev. C | Page 6 of 20
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.25 V (AD7788B and AD7789); V
DD
= 2.7 V to 5.25 V (AD7788A); GND = 0 V; REFIN(+) = 2.5 V; REFIN(−) = GND;
Input Logic 0 = 0 V; Input Logic 1 = V
DD
, unless otherwise noted.
Table 4.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(B Version) Unit Description
t
3
100 ns min SCLK high pulse width
t
4
100 ns min SCLK low pulse width
Read Operation
t
1
0 ns min
CS falling edge to DOUT/RDY active time
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
2
3
0 ns min SCLK active edge to data valid delay
4
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
5
5, 6
10 ns min
Bus relinquish time after
CS inactive edge
80
ns max
t
6
0 ns min
SCLK inactive edge to
CS inactive edge
t
7
10 ns min
SCLK inactive edge to DOUT/
RDY high
Write Operation
t
8
0 ns min
CS falling edge to SCLK active edge setup time
4
t
9
30 ns min Data valid to SCLK edge setup time
t
10
25 ns min Data valid to SCLK edge hold time
t
11
0 ns min
CS rising edge to SCLK edge hold time
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit of, and defined as, the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true
bus relinquish times of the device and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, the same data can be read again, if required, while
RDY
is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD7789BRM-REEL

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Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit SGL-Ch Ultra Low Power
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