AD7789BRMZ-REEL Datasheet AD7789BRMZ-REEL, AD7789BRMZ, AD7788BRMZ | P16-P18

AD7788/AD7789 Data Sheet

Rev. C | Page 16 of 20

Continuous Read Mode

Rather than write to the communications register each time a

conversion is complete to access the data, the AD7788/AD7789

can be placed in continuous read mode. By writing 001111XX

to the communications register, the user needs only to apply the

appropriate number of SCLK cycles to the ADC and the data-

word is automatically placed on the DOUT/

RDY

line when a

conversion is complete.

When DOUT/

RDY

goes low to indicate the end of a conver-

sion, sufficient SCLK cycles must be applied to the ADC and

the data conversion is placed on the DOUT/

RDY

line. When

the conversion is read, DOUT/

RDY

returns high until the next

conversion is available. In this mode, the data can be read only

once. Also, the user must ensure that the data-word is read

before the next conversion is complete.

If the data-word has not read the conversion before the completion

of the next conversion, or if insufficient serial clocks are applied

to the AD7788/AD7789 to read the word, the serial output

new conversion is placed in the output serial register.

To exit continuous read mode, the instruction 001110XX must

be written to the communications register while the DOUT/

RDY

pin is low. While in continuous read mode, the ADC

monitors activity on the DIN line so that it can receive the

instruction to exit continuous read mode. Additionally, a

reset occurs if 32 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is to be written to the device.

03539-011

DIN

SCLK

DOUT/RDY

0x3C

DATA DATA DATA

Figure 13. Continuous-Read Mode

Data Sheet AD7788/AD7789

Rev. C | Page 17 of 20

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7788/AD7789 have one differential analog input channel

that is connected to the modulator, thus, the input is unbuffered.

Note that this unbuffered input path provides a dynamic load to

the driving source. Therefore, resistor/capacitor combinations on

the input pins can cause dc gain errors, depending on the output

impedance of the source that is driving the ADC input. Table 13

shows the allowable external resistance/capacitance values such

that no gain error at the 16-bit level is introduced (AD7788).

Table 14 shows the allowable external resistance/capacitance

values such that no gain error at the 20-bit level is introduced

(AD7789).

Table 13. External R-C Combination for No 16-Bit Gain

Error (AD7788)

C (pF) R (Ω)

22.8 k

100 13.1 k

500 3.3 k

1000 1.8 k

5000 360

Table 14. External R-C Combination for No 20-Bit Gain

Error (AD7789)

C (pF) R (Ω)

50 16.7 k

100 9.6 k

500 2.2 k

1000 1.1 k

5000 160

The absolute input voltage includes the range between GND −

30 mV and V

+ 30 mV. The negative absolute input voltage

limit does allow the possibility of monitoring small true bipolar

signals with respect to GND.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the devices can accept either unipolar or

bipolar input voltage ranges. A bipolar input range does not

imply that the devices can tolerate large negative voltages with

respect to system GND. Unipolar and bipolar signals on the

AIN(+) input are referenced to the voltage on the AIN(−) input.

For example, if AIN(−) is 2.5 V and the ADC is configured for

unipolar mode, the input voltage range on the AIN(+) pin is

2.5 V to 5 V. If the ADC is configured for bipolar mode, the

analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/

unipolar option is chosen by programming the U/

bit in the

mode register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 000...000, a midscale voltage

resulting in a code of 100...000, and a full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

Code = 2

× (AIN/V

REF

)

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000...000, a zero differential input voltage resulting

in a code of 100...000, and a positive full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

Code = 2

N – 1

× ((AIN/V

REF

) + 1)

where:

AIN is the analog input voltage.

N = 16 for the AD7788, 24 for the AD7789.

REFERENCE INPUT

The AD7788/AD7789 have a fully differential input capability

for the channel. The common-mode range for these differential

inputs is from GND to V

. The reference input is unbuffered

and, therefore, excessive R-C source impedances introduce gain

errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is

2.5 V nominal, but the AD7788/AD7789 are functional with

reference voltages from 0.1 V to V

. In applications where the

excitation (voltage or current) for the transducer on the analog

input also drives the reference voltage for the devices, the effect

of the low frequency noise in the excitation source is removed

because the application is ratiometric. If the AD7788/AD7789

are used in a nonratiometric application, a low noise reference

should be used.

Recommended 2.5 V reference voltage sources for the AD7788/

AD7789 include the ADR381 and ADR391, because they are

low noise, low power references. If the analog circuitry uses a

2.5 V power supply, the reference voltage source requires some

headroom. In this case, a 2.048 V reference such as the ADR380

can be used. Again, these are low power, low noise references.

Also note that the reference inputs provide a high impedance,

dynamic load. Because the input impedance of each reference

input is dynamic, resistor/capacitor combinations on these

inputs can cause dc gain errors, depending on the output

impedance of the source that is driving the reference inputs.

AD7788/AD7789 Data Sheet

Rev. C | Page 18 of 20

Reference voltage sources like those recommended in the pre-

vious section (for example, ADR391) typically have low output

impedances and are, therefore, tolerant to having decoupling

capacitors on REFIN(+) without introducing gain errors in the

system. Deriving the reference input voltage across an external

resistor means that the reference input sees a significant external

source impedance. External decoupling on the REFIN pins is

not recommended in this type of circuit configuration.

MONITOR

Along with converting external voltages, the analog input

channel can be used to monitor the voltage on the V

pin.

When Bit CH1 and Bit CH0 in the communications register are

set to 1, the voltage on the V

pin is internally attenuated by 5

and the resultant voltage is applied to the Σ-Δ modulator using

an internal 1.17 V reference for analog-to-digital conversion.

This is useful because variations in the power supply voltage

can be monitored.

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs of the ADC are

differential, most of the voltages in the analog modulator are

common-mode voltages. The excellent common-mode rejection

of the device removes common-mode noise on these inputs.

The digital filter provides rejection of broadband noise on the

power supply, except at integer multiples of the modulator

sampling frequency. The digital filter also removes noise from

the analog and reference inputs, provided that these noise

sources do not saturate the analog modulator. As a result, the

AD7788/AD7789 are more immune to noise interference than

conventional high resolution converters. However, because the

resolution of the AD7788/AD7789 is so high, and the noise

levels from the AD7788/AD7789 are so low, care must be taken

with regard to grounding and layout.

The printed circuit board that houses the AD7788/AD7789

should be designed such that the analog and digital sections

are separated and confined to certain areas of the board. A

minimum etch technique is generally best for ground planes

because it gives the best shielding.

It is recommended that the AD7788/AD7789 GND pins be tied

to the AGND plane of the system. In any layout, it is important

that the user consider the flow of currents in the system, ensuring

that the return paths for all currents are as close as possible to

the paths the currents took to reach their destinations. Avoid

forcing digital currents to flow through the AGND sections of

the layout.

The AD7788/AD7789 ground plane should be allowed to run

under the devices to prevent noise coupling. The power supply

lines to the AD7788/AD7789 should use as wide a trace as

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals, such

as clocks, should be shielded with digital ground to avoid radiating

noise to other sections of the board, and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This reduces the effects of

feedthrough through the board. A microstrip technique is by far

the best, but it is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes, with signals placed on the solder side.

Good decoupling is important when using high resolution ADCs.

should be decoupled with a 10 µF tantalum in parallel with

0.1 µF capacitors to GND. To achieve the best from these

decoupling components, they should be placed as close as

possible to the device, ideally right up against the device. All

logic chips should be decoupled with 0.1 µF ceramic capacitors

to DGND.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

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Analog to Digital Converters - ADC 24-Bit SGL-Ch Ultra Low Power

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