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NB3N1900KMNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
NB3N1900K
www.onsemi.com
16
Table 23. SMBusTable: PLL MODE, AND FREQUENCY SELECT REGISTER
Byte 0 Pin # Name Control Function Type 0 1 Default
Bit 7 5 PLL Mode 1 PLL Operating Mode Rd back 1 R
See PLL Operating Mode
Readback Table
Latch
Bit 6 5
PLL Mode 0 PLL Operating Mode Rd back 0
R Latch
Bit 5 72/71 DIF_18_En Output Control overrides OE# pin RW Hi−Z Enable 1
Bit 4 70/69 DIF_17_En Output Control overrides OE# pin RW Hi−Z Enable 1
Bit 3 67/66 DIF_16_En Output Control overrides OE# pin RW Hi−Z Enable 1
Bit 2 Reserved 0
Bit 1 Reserved 0
Bit 0
4 100M_133M# Frequency Select Readback R 133 MHz 100 MHz Latch
Table 24. SMBusTable: OUTPUT CONTROL REGISTER
Byte 1 Pin # Name Control Function Type 0 1 Default
Bit 7 39/38 DIF_7_En Output Control overrides OE# pin RW
Hi−Z Enable
1
Bit 6 35/36 DIF_6_En Output Control overrides OE# pin RW 1
Bit 5 32/33 DIF_5_En Output Control overrides OE# pin RW 1
Bit 4 29/30 DIF_4_En Output Control overrides OE# pin RW 1
Bit 3 27/28 DIF_3_En Output Control overrides OE# pin RW 1
Bit 2 24/25 DIF_2_En Output Control overrides OE# pin RW 1
Bit 1 22/23 DIF_1_En Output Control overrides OE# pin RW 1
Bit 0
19/20 DIF_0_En Output Control overrides OE# pin RW 1
Table 25. SMBusTable: OUTPUT CONTROL REGISTER
Byte 2 Pin # Name Control Function Type 0 1 Default
Bit 7 65/64 DIF_15_En Output Control overrides OE# pin RW
Hi−Z
Enable
1
Bit 6 62/61 DIF_14_En Output Control overrides OE# pin RW 1
Bit 5 60/59 DIF_13_En Output Control overrides OE# pin RW 1
Bit 4 56/55 DIF_12_En Output Control overrides OE# pin RW 1
Bit 3 53/52 DIF_11_En Output Control overrides OE# pin RW 1
Bit 2 50/49 DIF_10_En Output Control overrides OE# pin RW 1
Bit 1 47/46 DIF_9_En Output Control overrides OE# pin RW 1
Bit 0
42/41 DIF_8_En Output Control overrides OE# pin RW 1
Table 26. SMBusTable: OUTPUT ENABLE PIN STATUS READBACK REGISTER
Byte 3 Pin # Name Control Function Type 0 1 Default
Bit 7 57 OE_RB12 Real Time readback of OE#12 R
OE# pin Low
OE# Pin Hig
h
Real time
Bit 6 54 OE_RB11 Real Time readback of OE#11 R Real time
Bit 5 51 OE_RB10 Real Time readback of OE#10 R Real time
Bit 4 48 OE_RB9 Real Time readback of OE#9 R Real time
Bit 3 43 OE_RB8 Real Time readback of OE#8 R Real time
Bit 2 40 OE_RB7 Real Time readback of OE#7 R Real time
Bit 1 37 OE_RB6 Real Time readback of OE#6 R Real time
Bit 0
34 OE_RB5 Real Time readback of OE#5 R Real time
NB3N1900K
www.onsemi.com
17
Table 27. SMBusTable: RESERVED REGISTER
Byte 4 Pin # Name Control Function Type 0 1 Default
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 0
Bit 2 Reserved 0
Bit 1 Reserved 0
Bit 0
Reserved 0
Table 28. SMBusTable: VENDOR & REVISION ID REGISTER
Byte 5 Pin # Name Control Function Type 0 1 Default
Bit 7 − RID3
REVISION ID
R
−
X
Bit 6 − RID2 R X
Bit 5 − RID1 R X
Bit 4 − RID0 R X
Bit 3 − VID3
VENDOR ID
R − − 1
Bit 2 − VID2 R − − 1
Bit 1 − VID1 R − − 1
Bit 0
− VID0 R − − 1
Table 29. SMBusTable: DEVICE ID
Byte 6 Pin # Name Control Function Type 0 1 Default
Bit 7 − Device ID 7 (MSB) R
Device ID is 120 decimal o
r
78 hex.
1
Bit 6 − Device ID 6 R 1
Bit 5 − Device ID 5 R 0
Bit 4 − Device ID 4 R 1
Bit 3 − Device ID 3 R 1
Bit 2 − Device ID 2 R 0
Bit 1 − Device ID 1 R 1
Bit 0
−
Device ID 0
R 1
Table 30. SMBusTable: BYTE COUNT REGISTER
Byte 7 Pin # Name Control Function Type 0 1 Default
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 − BC4
Writing to this register configures how
many bytes will be read back.
RW
Default value is 8 hex, so 9
bytes (0 to 8) will be read
back by default.
0
Bit 3 − BC3 RW 1
Bit 2 − BC2 RW 0
Bit 1 − BC1 RW 0
Bit 0
− BC0 RW 0
NB3N1900K
www.onsemi.com
18
Table 31. SMBusTable: RESERVED REGISTER
Byte 8 Pin # Name Control Function Type 0 1 Default
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 0
Bit 2 Reserved 0
Bit 1 Reserved 0
Bit 0
Reserved 0
DIF Reference Clock
Common Recommendations for Differential Routing Dimension or Value Unit
L1 length, route as non−coupled 50 W trace (Figure 6)
0.5 max inch
L2 length, route as non−coupled 50 W trace (Figure 6)
0.2 max inch
L3 length, route as non−coupled 50 W trace (Figure 6)
0.2 max inch
Rs (Figure 6) 33
W
Rt (Figure 6) 49.9
W
Down Device Differential Routing
L4 length, route as coupled microstrip 100 W differential trace (Figure 6)
2 min to 16 max inch
L4 length, route as coupled stripline 100 W differential trace (Figure 6)
1.8 min to 14.4 max inch
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100 W differential trace (Figure 7)
0.25 to 14 max inch
L4 length, route as coupled stripline 100 W differential trace (Figure 7)
0.225 min to 12.6 max inch
HCSL Output Buffer
L1
L1’
L2
Rs
L2’
Rs
L4
L4’
Rt Rt
PCI Express
Down Device
REF_CLK Input
L3’ L3
Figure 6. Down Device Routing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

NB3N1900KMNTXG

Mfr. #:
Buy NB3N1900KMNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 1:19 HCSL FANOUT BUF
Lifecycle:
New from this manufacturer.
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