NB3N1900K
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5
Table 7. PIN DESCRIPTION
Pin # Pin Name Pin Type Description
1 VDDA PWR 3.3 V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 IREF OUT
This pin establishes the reference for the differential current−mode output pairs. It
requires a fixed precision resistor to ground. 475 W is the standard value for 100 W
differential impedance. Other impedances require different values.
See data sheet.
4 100M_133M# IN
Input to select operating frequency
1 = 100.00 MHz, 0 = 133.33 MHz
5 HBW_BYP_LBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
6 PWRGD/PWRDN# IN
Notifies device to sample latched inputs and start up on first high assertion, or exit
Power Down Mode on subsequent assertions. Low enters Power Down Mode.
7 GND PWR Ground pin.
8 VDDR PWR
3.3 V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
9 CLK_IN IN 0.7 V Differential true input
10 CLK_IN# IN 0.7 V Differential complementary Input
11 SA_0 IN
SMBus address bit. This is a tri−level input that works in conjunction with the SA_1
to decode 1 of 9 SMBus Addresses.
12 SDA I/O Data pin of SMBus circuitry, 5V tolerant
13 SCL IN Clock pin of SMBus circuitry, 5V tolerant
14 SA_1 IN
SMBus address bit. This is a tri−level input that works in conjunction with the SA_0
to decode 1 of 9 SMBus Addresses.
15 NC N/A No Connection.
16 NC N/A No Connection.
17 FB_OUT# OUT
Complementary half of differential feedback output, provides feedback signal to the
PLL for synchronization with input clock to eliminate phase error.
18 FB_OUT OUT
True half of differential feedback output, provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
19 DIF0 OUT 0.7 V differential true clock output
20 DIF0# OUT 0.7 V differential complementary clock output
21 VDD PWR Power supply, nominal 3.3 V
22 DIF1 OUT 0.7 V differential true clock output
23 DIF1# OUT 0.7 V differential complementary clock output
24 DIF2 OUT 0.7 V differential true clock output
25 DIF2# OUT 0.7 V differential complementary clock output
26 GND PWR Ground pin.
27 DIF3 OUT 0.7 V differential true clock output
28 DIF3# OUT 0.7 V differential complementary clock output
29 DIF4 OUT 0.7 V differential true clock output
30 DIF4# OUT 0.7 V differential complementary clock output
31 VDD PWR Power supply, nominal 3.3 V
32 DIF5 OUT 0.7 V differential true clock output
33 DIF5# OUT 0.7 V differential complementary clock output
34 OE5# IN
Active low input for enabling DIF pair 5.
1 = disable outputs, 0 = enable outputs
35 DIF6 OUT 0.7 V differential true clock output
36 DIF6# OUT 0.7 V differential complementary clock output
37 OE6# IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
