SC628A
18
The I
2
C General Speci cation
The SC628A is a read-write slave-mode I
2
C device and
complies with the Philips I
2
C standard Version 2.1, dated
January 2000. The SC628A has four user-accessible
internal 8-bit registers. The I
2
C interface has been
designed for program exibility, supporting direct format
for write operation. Read operations are supported on
both combined format and stop separated format. While
there is no auto increment/decrement capability in the
SC628A I
2
C logic, a tight software loop can be designed
to randomly access the next register independent of
which register you begin accessing. The start and stop
commands frame the data-packet and the repeat start
condition is allowed if necessary.
SC628A Limitations to the I
2
C Speci cations
The SC628A only recognizes seven bit addressing. This
means that ten bit addressing and CBUS communication
are not compatible. The device can operate in either
standard mode (100kbit/s) or fast mode (400kbit/s).
Slave Address Assignment
The seven bit slave address is 0110 111x. The eighth bit is
the data direction bit. 0x6E is used for a write operation,
and 0x6F is used for a read operation.
Supported Formats
The supported formats are described in the following
subsections.
Direct Format — Write
The simplest format for an I
2
C write is direct format. After
the start condition [S], the slave address is sent, followed
by an eighth bit indicating a write. The SC628A I
2
C then
acknowledges that it is being addressed, and the master
responds with an 8 bit data byte consisting of the register
address. The slave acknowledges and the master sends
the appropriate 8 bit data byte. Once again the slave
acknowledges and the master terminates the transfer
with the stop condition [P].
Combined Format — Read
After the start condition [S], the slave address is sent,
followed by an eighth bit indicating a write. The SC628A
I
2
C then acknowledges that it is being addressed, and the
master responds with an 8 bit data byte consisting of the
register address. The slave acknowledges and the master
sends the repeated start condition [Sr]. Once again, the
slave address is sent, followed by an eighth bit indicating
a read. The slave responds with an acknowledge and the
previously addressed 8 bit data byte; the master then
sends a non-acknowledge (NACK). Finally, the master
terminates the transfer with the stop condition [P].
Stop Separated Reads
Stop-separated reads can also be used. This format
allows a master to set up the register address pointer for
a read and return to that slave at a later time to read the
data. In this format the slave address followed by a write
command are sent after a start [S] condition. The SC628A
then acknowledges it is being addressed, and the master
responds with the 8-bit register address. The master
sends a stop or restart condition and may then address
another slave. After performing other tasks, the master
can send a start or restart condition to the SC628A with
a read command. The device acknowledges this request
and returns the data from the register location that had
previously been set up.
Serial Interface
