Data Sheet HMC8401
Rev. 0 | Page 13 of 17
Figure 38. Output IP3 vs Frequency at Various V
GG
2 Voltages
Figure 39. P1dB vs. Frequency at Various V
GG
2 Voltages
Figure 40. P
SAT
vs. Frequency at Various V
GG
2 Voltages
IP3 (dBm)
FREQUENCY (GHz)
2 6 10 14 18 22 26 30
0
5
10
15
20
25
30
–2V
–1.8V
–1.6V
–1.4V
–1.2
–1V
0V
+1V
+2V
13850-038
P1dB (dBm)
FREQUENCY (GHz)
2 6 10 14 18 22 26 30
–2V
–1.8V
–1.6V
–1.4V
–1.2
–1V
+2V
0
4
8
12
16
20
24
13850-039
P
SAT
(dBm)
FREQUENCY (GHz)
2 6 10 14 18 22 26 30
–2V
–1.8V
–1.6V
–1.4V
–1.2
–1V
+2V
0
4
8
12
16
20
24
13850-040
HMC8401 Data Sheet
Rev. 0 | Page 14 of 17
THEORY OF OPERATION
The HMC8401 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a cascode distributed amplifier
with an integrated resistor for the drain. The cascode distributed
architecture uses a fundamental cell consisting of a stack of two
field effect transistors (FETs) with the source of the upper FET
connected to drain of the lower FET. The fundamental cell is then
duplicated several times with an RFIN transmission line intercon-
necting the gates of the lower FETs and an RFOUT transmission
line interconnecting the drains of the upper FETs.
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 41.
Figure 41. Architecture and Simplified Schematic
Though the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider tapped off of V
DD
, the V
GG
2 pad is
provided to allow the user an optional means of changing the
gate bias of the upper FETs. Adjustment of the V
GG
2 voltage
across the range from −2 V through +2.4 V changes the gate
bias of the upper FETs, thus affecting gain changes of
approximately 4 dB, depending on frequency. Increasing the
voltage applied to V
GG
2 increases the gain, while decreasing the
voltage decreases the gain. For the nominal V
DD
= 7.5 V, the
resulting V
GG
2 open circuit voltage is approximately 2.06 V.
A voltage applied to the V
GG
1 pad sets the gate bias of the lower
FETs, providing control of the drain current. Unlike the upper
FETs, a gate bias voltage for the lower FETs is not generated
internally. For this reason, the application of a bias voltage to the
V
GG
1 pad is required and not optional.
To operate the HMC8401 at voltages lower than the nominal 7.5 V,
use a bias tee to apply 5.25 V to the drain via the RFOUT pad.
When using this alternate bias configuration, leave the V
DD
pad
open and adjust V
GG
1 to obtain a nominal quiescent I
DD
= 60 mA.
Though data taken using the alternate bias configuration is not
presented on this data sheet, the resulting performance differs only
slightly from that obtained using the typical bias configuration. The
small signal gain is a few tenths of dB greater, the compression
characteristics are slightly harder, and the noise figure characteristics
remain mostly unchanged.
For additional information regarding this alternate bias
configuration, contact Analog Devices Applications.
13850-041
RFIN
V
GG
2
AC
G
RFOUT
V
GG
1
T-LINE
T-LINE
V
DD
ACG ACG
Data Sheet HMC8401
Rev. 0 | Page 15 of 17
APPLICATIONS INFORMATION
BIASING PROCEDURES
Capacitive bypassing is required for V
DD
and V
GG
1, as shown in
the typical application circuit in Figure 43. Gain control is
possible through the application of a dc voltage to V
GG
2. If gain
control is used, then V
GG
2 must be bypassed by 100 pF, 0.1 μF, and
4.7 μF capacitors. If gain control is not used, then V
GG
2 can be
either left open or capacitively bypassed as described.
The recommended bias sequence during power-up is as follows:
1. Set V
GG
1 to −2.0 V to pinch off the channels of the lower
FETs.
2. Set V
DD
to 7.5 V. Because the lower FETs are pinched off,
I
DQ
remains very low upon application of V
DD
.
3. Adjust V
GG
1 to be more positive until the desired quiescent
drain current is obtained.
4. Apply the RF input signal.
5. If the gain control function is to be used, apply to V
GG
2 a
voltage within the range of −2.0 V to +2.4 V until the
desired gain is achieved.
Use of the V
GG
2 (the gain control function) affects the drain
current.
The recommended bias sequence during power-down is as follows:
1. Turn of f the RF input signal.
2. Remove the V
GG
2 voltage or set it to 0 V.
3. Set V
GG
1 to −2.0 V to pinch off the channels of the lower
FETs.
4. Set V
DD
to 0 V.
5. Set V
GG
1 to 0 V.
Power-up and power-down sequences may differ from the ones
described, though care must always be taken to ensure adherence
to the values shown in the Absolute Maximum Ratings.
Unless otherwise noted, all measurements and data shown
were taken using the typical application circuit (see Figure 43),
configured as shown on the assembly diagram (see Figure 44)
and biased per the conditions in this section. The bias conditions
shown in this section are the operating points recommended to
optimize the overall performance. Operation using other bias
conditions may provide performance that differs from what is
shown in this data sheet. To obtain the best performance while
not damaging the device, follow the recommended biasing
sequence outlined in this section.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICs
Attach the die directly to the ground plane eutectically or with
conductive epoxy. To bring RF to and from the chip, use 50 Ω
microstrip transmission lines on 0.127 mm (5 mil) thick alumina
thin film substrates (see Figure 42).
Figure 42. Routing RF Signals with Molytab
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Handling Precautions
To avoid permanent damage, adhere to the following precautions:
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After the sealed
ESD protective bag is opened, store all die in a dry nitrogen
environment.
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
Mounting
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip
temperature at 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
Epoxy Die Attach
ABLETHERM 2600BT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
RF GROUND PLANE
0.05mm (0.002") THICK GaAs MMIC
WIRE BOND
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
0.150mm
(0.005”) THICK
MOLY TAB
0.076mm
(0.003")
13850-042

HMC8401-SX

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Amplifier Die Sales- 2 die pack
Lifecycle:
New from this manufacturer.
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