CY22050KFZXI Datasheet CY22050KFI, CY22050KFZXI, CY22050KFZXC | P1-P3

CY22050

One-PLL General-Purpose

Flash-Programmable Clock Generator

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07006 Rev. *O Revised January 28, 2015

One-PLL Gene ral-Purpose Flas h-Programmable Clock Generato r

Features

■ Integrated phase-locked loop (PLL)

■ Commercial and Industrial operation

■ Flash-programmable

■ Field-programmable

■ Low-skew, low-jitter, high-accuracy outputs

■ 3.3 V operation with 2.5 V output option

■ 16-pin TSSOP package (CY22050)

■ Input frequency range:

❐ 8 MHz–30 MHz (external crystal)

❐ 1 MHz–133 MHz (driven clock)

■ Output frequency range:

❐ Commercial temperature

• 8 kHz–200 MHz (3.3 V)

• 8 kHz–166.6 MHz (2.5 V)

❐ Industrial temperature

• 8 kHz–166.6 MHz (3.3 V)

• 8 kHz–150 MHz (2.5 V)

Functional Description

The CY22050 is programmable clock generator for use in

networking, telecommunication, datacom, and other

general-purpose applications. The CY22050 offers up to six

configurable outputs in a 16-pin TSSOP, running off a 3.3 V

power supply. The on-chip reference oscillator is designed to run

off an 8–30-MHz crystal, or a 1–133-MHz external clock signal.

The CY22050 has a single PLL driving 6 programmable output

clocks. The output clocks are derived from the PLL or the

reference frequency (REF). Output post dividers are available for

either. Four of the outputs can be set as 3.3 V or 2.5 V, for use

in a wide variety of portable and low-power applications.

For a complete list of related documentation, click here.

XIN

XOUT

Divider

PLL

OSC.

LCLK3

VCO

VDDL

AVSS



AVDD

VSS

LCLK2

LCLK4

CLK5

CLK6

VSSLVDD

Bank 1

Divider

Bank 2

Output

Select

PWRDWN

LCLK1

Matrix

Logic Block Diagram

CY22050

Document Number: 38-07006 Rev. *O Page 2 of 15

Contents

Pin Configuration .............................................................3

Pin Definitions ..................................................................3

Programming Description ............................................... 4

Field Programming the CY22050F ..............................4

CyberClocks Software .............................................. 4

CY3672 Development Kit ............................................ 4

Applications ......................................................................4

Controlling Jitter ..........................................................4

CY22050 Frequency Calculation .....................................5

Clock Output Settings: Crosspoint Switch Matrix ........ 5

Reference Crystal Input ...................................................6

Crystal Drive Level and Power .................................... 6

Absolute Maximum Conditions .......................................6

Recommended Operating Conditions ............................7

Recommended Crystal Specifications ...........................7

DC Electrical Characteristics .......................................... 8

AC Electrical Characteristics .......................................... 8

Test Circuit ........................................................................ 9

Switching Waveforms ...................................................... 9

Ordering Information ...................................................... 10

Possible Configurations ............................................. 10

Ordering Code Definitions ......................................... 10

16-pin TSSOP Package Characteristics ....................... 11

Package Drawing and Dimensions ............................... 11

Acronyms ........................................................................ 12

Document Conventions ................................................. 12

Units of Measure ....................................................... 12

Document History Page ................................................. 13

Sales, Solutions, and Legal Information ...................... 15

Worldwide Sales and Design Support ....................... 15

Products .................................................................... 15

PSoC® Solutions ...................................................... 15

Cypress Developer Community ................................. 15

Technical Support ..................................................... 15

CY22050

Document Number: 38-07006 Rev. *O Page 3 of 15

Pin Configuration

Figure 1. 16-pin TSSOP pinout

VSS

VSSL

LCLK1

XIN

XOUT

VDD

PWRDWN

AVSS

LCLK3

LCLK2

CLK6

CLK5

AVDD

VDDL

LCLK4

Pin Definitions

Name Pin Number Description

XIN 1 Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).

Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on

manufacturer, process, performance, or quality.

VDD 2 3.3 V voltage supply

AVDD 3 3.3 V analog voltage supply

PWRDWN

[1]

4 Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode.

AVSS 5 Analog ground

VSSL 6 LCLK ground

LCLK1 7 Configurable clock output 1 at V

DDL

level (3.3 V or 2.5 V)

LCLK2 8 Configurable clock output 2 at V

DDL

level (3.3 V or 2.5 V)

LCLK3 9 Configurable clock output 3 at V

DDL

level (3.3 V or 2.5 V)

[1]

10 Output Enable. When pin 10 is driven LOW, all outputs are three-stated.

VDDL 11 LCLK voltage supply (2.5 V or 3.3 V)

LCLK4 12 Configurable clock output 4 at V

DDL

level (3.3 V or 2.5 V)

VSS 13 Ground

CLK5 14 Configurable clock output 5 (3.3 V)

CLK6 15 Configurable clock output 6 (3.3 V)

XOUT

[2]

16 Reference output

Notes

1. The CY22050 has no internal pull up or pull down resistors. PWRDWN

and OE pins need to be driven as appropriate or tied to power or ground.

2. Float XOUT if XIN is driven by an external clock source.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

CY22050KFZXI

Mfr. #:

Buy CY22050KFZXI

Manufacturer:

Cypress Semiconductor

Description:

Phase Locked Loops - PLL Flash Clock Gen 1MHz-133MHz

Lifecycle:

New from this manufacturer.

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CY22050KFZXI

CY22050KFZXI

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