Document Number: 38-07006 Rev. *O Page 8 of 15
DC Electrical Characteristics
Parameter
[4]
Description Condition Min Typ Max Unit
I
OH3.3
Output High Current V
OH
= V
DD
– 0.5 V, V
DD
/V
DDL
= 3.3 V 12 24 – mA
I
OL3.3
Output Low Current V
OL
= 0.5 V, V
DD
/V
DDL
= 3.3 V 12 24 – mA
I
OH2.5
Output High Current V
OH
= V
DDL
– 0.5 V, V
DDL
= 2.5 V 8 16 – mA
I
OL2.5
Output Low Current V
OL
= 0.5 V, V
DDL
= 2.5 V 8 16 – mA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7 – 1.0 V
DD
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
0–0.3V
DD
I
VDD
[5, 6]
Supply Current
AV
DD
/V
DD
Current –45–mA
I
VDDL3.3
[5, 6]
Supply Current
V
DDL
Current (V
DDL
= 3.465 V) – 25 – mA
I
VDDL2.5
[5, 6]
Supply Current
V
DDL
Current (V
DDL
= 2.625 V) – 17 – mA
I
DDS
Power Down Current V
DD
= V
DDL
= AV
DD
= 3.465 V – – 50 A
I
OHZ
I
OLZ
Output Leakage V
DD
= V
DDL
= AV
DD
= 3.465 V – – 10 A
AC Electrical Characteristics
Parameter
[4]
Description Condition Min Typ Max Unit
t
1
Output frequency,
commercial temperature
Clock output limit, 3.3 V 0.008 (8 kHz) – 200 MHz
Clock output limit, 2.5 V 0.008 (8 kHz) – 166.6 MHz
Output frequency,
industrial temperature
Clock output limit, 3.3 V 0.008 (8 kHz) – 166.6 MHz
Clock output limit, 2.5 V 0.008 (8 kHz) – 150 MHz
t
2
Output duty cycle Duty cycle is defined in Figure 4, t
1
/t
2
,
f
OUT
> 166 MHz, 50% of V
DD
40 50 60 %
Duty cycle is defined in Figure 4, t
1
/t
2
,
f
OUT
< 166 MHz, 50% of V
DD
45 50 55 %
t
3LO
Rising edge slew rate
(V
DDL
= 2.5 V)
Output clock rise time, 20%–80% of V
DDL
,
defined in Figure 5
0.6 1.2 – V/ns
t
4LO
Falling edge slew rate
(V
DDL
= 2.5 V)
Output clock fall time, 80%–20% of V
DDL
,
defined in Figure 5
0.6 1.2 – V/ns
t
3HI
Rising edge slew rate
(V
DDL
= 3.3 V)
Output clock rise time, 20%–80% of
V
DD
/V
DDL
, defined in Figure 5
0.8 1.4 – V/ns
t
4HI
Falling edge slew rate
(V
DDL
= 3.3 V)
Output clock fall time, 80%–20% of
V
DD
/V
DDL
, defined in Figure 5
0.8 1.4 – V/ns
t
5
[7]
Skew
Output-output skew between related
outputs
––250ps
t
6
[8]
Clock jitter
Peak-to-peak period jitter (see Figure 6) – 250 – ps
t
10
PLL lock time – 0.30 3 ms
Notes
4. Not 100% tested, guaranteed by design.
5. I
VDD
currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. All outputs are
loaded with 15 pF.
6. Use CyClocksRT to calculate actual I
VDD
and I
VDDL
for specific output frequency configurations.
7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information.
8. Jitter measurement will vary. Actual jitter is dependent on X
IN
jitter and edge rate, number of active outputs, output frequencies, V
DDL
(2.5 V or 3.3 V), temperature,
and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com,
or contact your local Cypress Field Applications Engineer.
