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LTC1645CS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
13
LTC1645
1645fa
voltage on the external capacitor C
TIMER
starts to ramp up
with a slope dv/dt = 2µA/C
TIMER
. When the voltage reaches
the trip point (1.23V), the timer is reset by pulling the
TIMER pin back to ground. The timer period is
t = (1.23V • C
TIMER
)/2µA. For a 200ms delay, use a 0.33µF
capacitor.
Electronic Circuit Breaker
The LTC1645 features an electronic circuit breaker func-
tion that protects against short circuits or excessive out-
put currents. By placing sense resistors between the
supply inputs and sense pins of the supplies, the circuit
breaker trips whenever the voltage across either sense
resistor is greater than 50mV for more than 1.5µs. If the
circuit breaker trips, both GATE
pins are immediately
pulled to ground and the external N-channels FETs are
quickly turned off (time point 6 in Figure 12). The circuit
breaker resets and another timing cycle starts by taking
the ON pin below 0.4V and then high as shown at time
point 7.
At the end of the timer cycle (time point 8), the charge
pump turns on again. If the circuit breaker feature is not
required, short the SENSE
n
pin to V
CC
n
.
If the 1.5µs response time is too fast to reject supply noise,
add external resistors and capacitors R
F
and C
F
to the
sense circuit as shown in Figure 13.
The ON Pin
The ON pin is used to control system operation as shown
in Figure 14. At time point 1, the board makes connection
and the supplies power up the chip. At time point 2, the ON
pin goes high and a timer cycle starts as long as both V
CC
pins are higher than the undervoltage lockout trip point
(2.23V for V
CC1
and 1.12V for V
CC2
) and an overcurrent
fault is not detected. At the end of the timer cycle (time
point 3), the charge pump is turned on and the GATE
n
pin
voltages start to ramp up with the output supply voltages,
V
OUT
n
, following one gate-to-source voltage drop lower.
At time point 4, V
OUT2
reaches its power-good trip level
(this example assumes the FB pin resistive divider is
connected to V
OUT2
) and a timing cycle starts. At the end
of the timing cycle (time point 5), RESET goes high and the
power-up process is complete.
APPLICATIO S I FOR ATIO
WUUU
Figure 13. Extending the Short-Circuit Protection Delay
Figure 12. Current Fault Timing
Figure 14. ON Pin Waveforms
1645 F14
ON
0.8V
0.4V
0V
2V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GATE1
GATE2
V
OUT1
V
OUT2
TIMER
V
CC
n
RESET
RAMPING UP AND
DOWN TOGETHER
RAMPING UP AND
TURNING OFF FAST
RAMPING UP AND
DOWN SEPARATELY
SENSE
n
LTC1645
GATE
n
V
CC
n
1645 G13
C
F
R
F
RESET
V
OUT
n
GATE
n
1645 F12
TIMER
ON
V
CC
n
– V
SENSE
n
V
CC
n
12 3 4
RAMPING UP
RESET FAULT
AND RAMP UP
CURRENT
FAULT
56 7 89 10
14
LTC1645
1645fa
An external hard reset is initiated at time point 6. The ON
pin is forced below 0.8V but above 0.4V, and the GATE
n
pin voltages start to ramp down. V
OUT
n
also starts to ramp
down, and RESET goes low when V
OUT2
drops below the
power-good trip level at time point 7.
Time points 8 to 15 are similar to time points 1 to 7, except
the ON pin’s different voltage thresholds are used to ramp
V
OUT1
and V
OUT2
separately. At time point 8, the ON pin
goes above 0.8V but below 2V, and one timing cycle later
(time point 9) GATE1 begins to ramp up with V
OUT1
following one gate-to-source voltage drop lower. At time
point 10, the ON pin goes above 2V and GATE2 immedi-
ately begins ramping up with V
OUT2
following one gate-to-
source voltage drop lower. As soon as V
OUT2
reaches its
power-good trip level at time point 11, a timing cycle
starts. At the end of the timing cycle (time point 12),
RESET goes high and the power-up process is complete.
The ON pin is forced below 2V but above 0.8V at time point
13 and the GATE2 pin voltage starts to ramp down. V
OUT2
also starts to ramp down and RESET goes low when V
OUT2
drops below the power-good trip level at time point 14.
When the ON pin goes below 0.8V but above 0.4V at time
point 15, GATE1 and V
OUT1
ramp down.
Time points 16 to 19 show the same power-up sequence
as time points 2 to 5, while time point 20 demonstrates the
GATE
n
pins being pulled immediately to ground (instead
of ramping down) by the ON pin going below 0.4V.
Power Supply Tracking and Sequencing Applications
The LTC1645 is able to sequence V
OUT
n
in a number of
ways, including ramping V
OUT1
up first and down last;
ramping V
OUT1
up first and down first; ramping V
OUT1
up
first and V
OUT1
and V
OUT2
down together; and ramping
V
OUT1
and V
OUT2
up and down together.
Figure 15 shows an application ramping V
OUT1
and V
OUT2
up and down together. The ON pin must reach 0.8V to
ramp up V
OUT1
and V
OUT2
. The spare comparator pulls the
ON pin low until V
CC2
is above 2.3V, and the ON pin cannot
reach 0.8V before V
CC1
is above 3V. Thus, both input
supplies must be within regulation before a timing cycle
can start. At the end of the timing cycle, the output voltages
ramp up together. If either input supply falls out of
regulation, the gates of Q1 and Q2 are pulled low together.
Figure 16 shows an oscilloscope photo of the circuit in
Figure 15.
APPLICATIO S I FOR ATIO
WUUU
Figure 15. Ramping 3.3V and 2.5V Up and Down Together
Q1
1/2 Si4920DY
Q2
1/2 Si4920DY
0.01Ω*
0.01Ω*
10Ω
10Ω
1.18k
1%
10k
1.37k
1%
0.1µF
25V
0.33µF
*WSL1206-01-1% (VISHAY DALE)
C
LOAD1
C
LOAD2
D1
1N4002
D3
MBR0530T1
D2
1N4002
1
2
3
8
9
6
5
11
7
13 1214
BOTH CURRENT LIMITS: 5A
10
4
V
CC1
ON
FAULT
TIMER GND
SENSE1 GATE2GATE1
V
CC2
TRIP
POINT:
3V
V
IN1
3.3V
V
IN2
2.5V
V
OUT1
3.3V
2.5A
V
OUT2
2.5V
2.5A
µP RESET
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
1645 F15
RESET
+
+
1.18k
1%
4.99k
1%
10k
1.37k
1%
1.82k
1%
15
LTC1645
1645fa
V
IN2
5V/DIV
V
IN1
5V/DIV
V
OUT2
5V/DIV
V
OUT1
5V/DIV
TIMER
2V/DIV
RESET
5V/DIV
Figure 16. Ramping 3.3V and 2.5V Up and Down Together
APPLICATIO S I FOR ATIO
WUUU
This circuit guarantees that: (1) V
OUT1
never exceeds
V
OUT2
by more than 1.2V, and (2) V
OUT2
is never greater
than V
OUT1
by more than 0.4V. On power-up, V
OUT1
and
V
OUT2
ramp up together. On power-down, the LTC1645
turns off Q1 and Q2 simultaneously. Charge remains
stored on C
LOAD1
and C
LOAD2
and the output voltages will
vary depending on the loads. D1 and D2 turn on at ≈1V
(≈0.5V each), ensuring condition 1 is satisfied, while D3
prevents violations of condition 2. Different diodes may be
necessary for different output voltage configurations.
Barring an overvoltage condition at the input(s), the only
time these diodes might conduct current is during a
power-down event, and then only to discharge C
LOAD1
or
C
LOAD2
. In the case of an input overvoltage condition that
causes excess current to flow, the circuit breaker will trip
if the current limit level is set appropriately.
Figure 17 shows an application circuit where V
OUT1
ramps up before V
OUT2
. V
OUT1
is initially discharged and
D1 is reverse-biased, thus the voltage at the ON pin is
determined only by V
CC1
through the resistor divider R1
and R2. The voltage at the ON pin exceeds 0.8V if V
CC1
is
above 4.6V and V
OUT1
begins to ramp up after a timing
cycle. As V
OUT1
ramps up, D1 becomes forward-biased
and pulls the ON pin above 2V when V
OUT1
≈ 4.5V. This
turns on GATE2 and V
OUT2
ramps up. The FB comparator
monitors V
OUT2
, and the spare comparator monitors
V
OUT1
with R
HYST
creating ≈50mV of hysteresis.
Power Supply Multiplexer
Using back-to-back FETs, the LTC1645 can Hot Swap two
supplies to the same output, automatically selecting the
primary supply if present or the secondary supply if the
primary supply is not available. Referring to Figure 18, a
diode-or circuit provides power to the LTC1645 if either
supply is up. Schottky diodes are used to prevent the
voltage at V
CC1
from approaching the undervoltage lock-
out threshold. This application assumes that if a supply is
not present, the supply input is floating.
If only the 3.3V supply is present, the voltage at the COMP
+
pin is below the trip point and COMPOUT pulls the base of
Q3 low, allowing the GATE1 pin to ramp up normally. The
voltage at the ON pin exceeds 0.8V if the 3.3V supply is
greater than 3V, ramping up GATE1 and turning on Q1A and
Q1B. The ON pin does not exceed 2V (unless the 3.3V supply
exceeds 7.5V!), keeping GATE2 low and Q2A and Q2B off.
If only the 5V supply is present or if both supplies are
present, the COMP
+
pin is above 1.238V and COMPOUT
allows the base of Q3 to be pulled high by R2. This turns
Q3 on, keeping GATE1 low and Q1A and Q1B off. The
voltage at the ON pin is pulled above 2V by R1 and GATE2
turns Q2A and Q2B on.
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LTC1645CS8#PBF

Mfr. #:
Buy LTC1645CS8#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers 2x-Ch Hot Swap Cntr/Pwr Sequencer
Lifecycle:
New from this manufacturer.
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