LT1940/LT1940L
13
1940fa
Soft-Start and Shutdown
The RUN/SS (Run/Soft-Start) pins are used to place the
individual switching regulators and the internal bias cir-
cuits in shutdown mode. They also provide a soft-start
function. To shut down either regulator, pull the RUN/SS
pin to ground with an open-drain or collector. If both
RUN/SS pins are pulled to ground, the LT1940 enters its
shutdown mode with both regulators off and quiescent
current reduced to ~30µA. Internal 2µA current sources
pull up on each pin. If either pin reaches ~0.5V, the internal
bias circuits start and the quiescent current increases to
~3.5mA.
If a capacitor is tied from the RUN/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This voltage clamps the V
C
pin, limiting the peak
switch current and therefore input current during start up.
A good value for the soft-start capacitor is C
OUT
/10,000,
where C
OUT
is the value of the output capacitor.
The RUN/SS pins can be left floating if the shutdown
feature is not used. They can also be tied together with a
single capacitor providing soft-start. The internal current
sources will charge these pins to ~2.5V.
The RUN/SS pins provide a soft-start function that limits
peak input current to the circuit during start-up. This helps
to avoid drawing more current than the input source can
supply or glitching the input supply when the LT1940 is
enabled. The RUN/SS pins do not provide an accurate
delay to start or an accurately controlled ramp at the
output voltage, both of which depend on the output
capacitance and the load current. However, the power
good indicators can be used to sequence the two outputs,
as described below.
Power Good Indicators
The PG pin is the open collector output of an internal
comparator. PG remains low until the FB pin is within 10%
of the final regulation voltage. Tie the PG pin to any supply
with a pull-up resistor that will supply less than 250µA.
Note that this pin will be open when the LT1940 is placed
in shutdown mode (both RUN/SS pins at ground) regard-
less of the voltage at the FB pin. Power good is valid when
the LT1940 is enabled (either RUN/SS pin is high) and V
IN
is greater than ~2.4V.
Output Sequencing
The PG and RUN/SS pins can be used to sequence the two
outputs. Figure 5 shows several circuits to do this. In each
case channel 1 starts first. Note that these circuits se-
quence the outputs during start-up. When shut down the
two channels turn off simultaneously.
In Figure 5a, a larger capacitor on RUN/SS2 delays chan-
nel 2 with respect to channel 1. The soft-start capacitor on
RUN/SS2 should be at least twice the value of the capacitor
on RUN/SS1. A larger ratio may be required, depending on
the output capacitance and load on each channel. Make
sure to test the circuit in the system before deciding on
final values for these capacitors.
The circuit in Figure 5b requires the fewest components,
with both channels sharing a single soft-start capacitor.
The power good comparator of channel 1 disables channel
2 until output 1 is in regulation.
For independent control of channel 2, use the circuit in
Figure 5c. The capacitor on RUN/SS1 is smaller than the
capacitor on RUN/SS2. This allows the LT1940 to start up
and enable its power good comparator before RUN/SS2
gets high enough to allow channel 2 to start switching.
Channel 2 only operates when it is enabled with the
external control signals and output 1 is in regulation.
The circuit in Figure 5a leaves both power good indicates
free. However, the circuits in Figures 5b and 5c have
another advantage. As well as sequencing the two outputs
at start-up, they also disable channel 2 if output 1 falls out
of regulation (due to a short circuit or a collapsing input
voltage).
Finally, be aware that the circuit in Figure 5d does not
work, because the power good comparators are disabled
in shutdown. When the system is placed in shutdown
mode by pulling down on RUN/SS1, then output 1 will go
low, PG1 will pull down on RUN/SS2, and the LT1940 will
enter its low current shutdown state. This disables PG1,
and RUN/SS2 ramps up again to enable the LT1940. The
circuit will oscillate and pull extra current from the input.
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LT1940/LT1940L
14
1940fa
Shorted Input Protection
If the inductor is chosen so that it won’t saturate exces-
sively, the LT1940 will tolerate a shorted output. There is
another situation to consider in systems where the output
will be held high when the input to the LT1940 is absent.
If the V
IN
and one of the RUN/SS pins are allowed to float,
then the LT1940’s internal circuitry will pull its quiescent
current through its SW pin. This is fine if your system can
tolerate a few mA of load in this state. With both RUN/SS
pins grounded, the LT1940 enters shutdown mode and
the SW pin current drops to ~30µA. However, if the V
IN
pin
is grounded while the output is held high, then parasitic
diodes inside the LT1940 can pull large currents from the
output through the SW pin and the V
IN
pin. A Schottky
diode in series with the input to the LT1940 will protect the
LT1940 and the system from a shorted or reversed input.
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Figure 5. Several Methods of Sequencing the Two Outputs. Channel 1 Starts First.
Figure 6. Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 7
shows the high-di/dt paths in the buck regulator circuit.
Note that large, switched currents flow in the power
switch, the catch diode and the input capacitor. The loop
formed by these components should be as small as
possible. These components, along with the inductor and
output capacitor, should be placed on the same side of the
circuit board, and their connections should be made on
that layer. Place a local, unbroken ground plane below
these components, and tie this ground plane to system
ground at one location, ideally at the ground terminal of the
output capacitor C2. Additionally, the SW and BOOST
nodes should be kept as small as possible. Figure 8 shows
recommended component placement with trace and via
locations.
OFF
1940 F05
RUN/SS1
PG1
ON
GND
OFF
RUN/SS1
ON
GND
RUN/SS2
OFF
RUN/SS1
ON
OFF2
ON2
GND
RUN/SS2
RUN/SS2
V
C2
PG1
1nF 1nF
1nF
2.2nF
1nF
1.5nF 1.5nF
(5b) Fewest Components
(5c) Independent Control of Channel 2
OFF
RUN/SS1
ON
GND
RUN/SS2
PG1
(5d) Doesn't Work !
(5a) Channel 2 is Delayed
V
IN
V
IN
V
OUT
SW
LT1940
D4
PARASITIC DIODE
1940 F06
LT1940/LT1940L
15
1940fa
Thermal Considerations
The PCB must also provide heat sinking to keep the
LT1940 cool. The exposed metal on the bottom of the
package must be soldered to a ground plane. This ground
should be tied to other copper layers below with thermal
vias; these layers will spread the heat dissipated by the
LT1940. Place additional vias near the catch diodes.
Adding more copper to the top and bottom layers and tying
this copper to the internal planes with vias can reduce
thermal resistance further. With these steps, the thermal
resistance from die (or junction) to ambient can be re-
duced to θ
JA
= 45°C/W.
The power dissipation in the other power components—
catch diodes, boost diodes and inductors,␣ cause addi-
tional copper heating and can further increase what the IC
sees as ambient temperature. See the LT1767 data sheet’s
Thermal Considerations section.
Single, Low-Ripple 2.8A Output
The LT1940 can generate a single, low-ripple 2.8A output
if the outputs of the two switching regulators are tied
together and share a single output capacitor. By tying the
two FB pins together and the two V
C
pins together, the two
channels will share the load current. There are several
advantages to this two-phase buck regulator. Ripple cur-
rents at the input and output are reduced, reducing voltage
ripple and allowing the use of smaller, less expensive
Figure 8. A Good PCB Layout Ensures Proper Low EMI Operation
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Figure 7. Subtracting the Current when the Switch is ON (a) From the Current when the Switch is OFF (b) Reveals the Path
of the High Frequency Switching Current (c) Keep This Loop Small. The Voltage on the SW and BOOST Nodes will also be
Switched; Keep these Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane.
V
IN
SW
GND
(7a)
V
IN
V
SW
C1 D1 C2
1940 F07
L1
SW
GND
(7c)
V
IN
SW
GND
(7b)
I
C1
VIA TO LOCAL GROUND PLANE
VIA TO V
IN
1940 F08
GNDV
OUT1
V
OUT2

LT1940EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 1.4A Step-dn DC/DC Converter
Lifecycle:
New from this manufacturer.
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