6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
6
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables (Input)
(7)
R/W
L
R/W
R
Read/Write Enable (Input)
OE
L
OE
R
Output Enable (Input)
A
0L
- A
17L
(6)
A
0R
- A
17R
(6)
Address (Input)
I/O
0L
- I/O
35L
I/O
0R
- I/O
35R
Data Input/Output
CLK
L
CLK
R
Clock (Input)
PL/FT
L
PL/FT
R
Pipeline/Flow-Through (Input)
ADS
L
ADS
R
Address Strobe Enable (Input)
CNTEN
L
CNTEN
R
Counter Enable (Input)
REPEAT
L
REPEAT
R
Counter Repeat
(3)
BE
0L
- BE
3L
BE
0R
- BE
3R
Byte Enables (9-bit bytes) (Input)
(7)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(1)
(Input)
OPT
L
OPT
R
Option for selecting V
DDQX
(1,2)
(Input)
ZZ
L
ZZ
R
Sleep Mode pin
(4)
(Input)
V
DD
Power (2.5V)
(1)
(Input)
V
SS
Ground (0V) (Input)
TDI
(5)
Test Data Input
TDO
(5)
Test Data Output
TCK
(5)
Test Logic Clock (10MHz) (Input)
TMS
(5)
Test Mode Select (Input)
TRST
(5)
Reset (Initialize TAP Controller) (Input)
INT
L
INT
R
Interrupt Flag (Output)
COL
L
COL
R
Collision Alert (Output)
5666 tbl 01
NOTES:
1. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEAT
X is asserted, the counter will reset to the last valid address loaded
via ADS
X.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Due to limited pin count, JTAG is not supported in the DR208 package.
6. Address A
17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x are
NC's for the IDT 70T3589.
7. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH, i.e., the
signals take two cycles to deselect.
