6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
7
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/W ZZ
Byte 3
I/O
27-3 5
Byte 2
I/O
18-2 6
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down
X
X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down
X
L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected
X
L H H H H L L L High-Z High-Z High-Z D
IN
Write to Byte 0 Only
X
LHHHLHL LHigh-ZHigh-Z D
IN
High-Z Write to Byte 1 Only
X
LHHLHHL LHigh-Z D
IN
High-Z High-Z Write to Byte 2 Only
X
LHLHHHL L D
IN
High-Z High-Z High-Z Write to Byte 3 Only
X
L H H H L L L L High-Z High-Z D
IN
D
IN
Write to Lower 2 Bytes Only
X
LHLLHHL L D
IN
D
IN
High-Z High-Z Write to Upper 2 bytes Only
X
LHLLLLLL D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
L H H H H L H L High-Z High-Z High-Z D
OUT
Read Byte 0 Only
L
LHHHLHHLHigh-ZHigh-Z D
OUT
High-Z Read Byte 1 Only
L
LHHLHHHLHigh-Z D
OUT
High-Z High-Z Read Byte 2 Only
L
LHLHHHHL D
OUT
High-Z High-Z High-Z Read Byte 3 Only
L
L H H H L L H L High-Z High-Z D
OUT
D
OUT
Read Lower 2 Bytes Only
L
LHLLHHHL D
OUT
D
OUT
High-Z High-Z Read Upper 2 Bytes Only
L
LHLLLLHL D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
X X X X X X X L High-Z High-Z High-Z High-Z Outputs Disabled
X X X X X X X X X H High-Z High-Z High-Z High-Z Sleep Mode
5666 tb l 0 2
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
0, CE1 and BEn
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS CNTEN REPEAT
(6 )
I/O
(3 )
MODE
An X An
L
(4 )
XHD
I/O
(n) External Address Used
XAnAn + 1
H L
(5)
HD
I/O
(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1
HH HD
I/O
(n+1) E xternal Address BlockedCounter disabled (An + 1 reused)
XXAn
XX L
(4)
D
I/O
(n) Counte r Set to last valid ADS load
5666 tbl 03
6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
8
Recommended Operating
Temperature and Supply Voltage
(1)
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Grade
Ambient
Temperature GND V
DD
Commercial 0
O
C to +70
O
C0V2.5V
+
100mV
Industrial -40
O
C to +85
O
C0V2.5V
+
100mV
5666 tbl 04
Recommended DC Operating
Conditions with V
DDQ at 3.3V
NOTES:
1. V
IL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. V
IH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to V
DD (2.5V), and VDDQX for that port must be supplied as indicated
above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(Address, Control
&Data I/O Inputs)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input High Voltage
_
JTAG
1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, PIPE/FT
V
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Inp ut Low Voltage -0.3
(1)
____
0.8 V
V
IL
Inp ut Low Voltage -
ZZ, OPT, PIPE/FT
-0.3
(1)
____
0.2 V
5666 tbl 05b
Recommended DC Operating
Conditions with V
DDQ at 2.5V
NOTES:
1. V
IL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. V
IH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to V
ss(0V), and VDDQX for that port must be supplied as indicated
above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
2.4 2.5 2.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Volltage
(Address, Control &
Data I/O Inputs)
(3)
1.7
____
V
DDQ
+ 100mV
(2)
V
V
IH
Input High Voltag e
_
JTAG
1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, PIPE/FT
V
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Input Low Voltag e -0.3
(1)
____
0.7 V
V
IL
Input Low Voltag e -
ZZ, OPT, PIPE/FT
-0.3
(1)
____
0.2 V
5666 tbl 05a
6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
9
Absolute Maximum Ratings
(1)
Symbol Rating Commercial
& Industrial
Unit
V
TE RM
(V
DD
)
V
DD
Terminal Voltage
with Respect to GND
-0.5 to 3.6 V
V
TE RM
(2 )
(V
DDQ
)
V
DDQ
Terminal Voltage
with Respect to GND
-0.3 to V
DDQ
+ 0.3 V
V
TERM
(2)
(INPUTS and I/O's)
Inp ut and I/O Terminal
Voltage with Respect to GND
-0.3 to V
DDQ
+ 0.3 V
T
BIAS
(3 )
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -65 to +150
o
C
T
JN
Junction Temperature +150
o
C
I
OUT
(For V
DDQ
=
3.3V) DC Output Current 50 mA
I
OUT
(For V
DDQ
=
2.5V) DC Output Current 40 mA
5666 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed V
DDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT also references CI/O.
Capacitance
(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol Parameter Conditions
(2 )
Max. Unit
C
IN
Inp ut Capacitance V
IN
= 3dV 8 pF
C
OUT
(3)
Output Capacitance V
OUT
= 3dV 10.5 pF
5666 tbl 07
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
Symbol Parameter Test Conditions
70T3519/99/89S
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
DDQ
= Max., V
IN
= 0V to V
DDQ
___
10 µA
|I
LI
| JTAG & ZZ Input Leakage Current
(1,2)
V
DD =
Max.
,
V
IN
= 0V to V
DD
___
±30 µA
|I
LO
| Output Leakage Current
(1,3)
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DDQ
___
10 µA
V
OL
(3.3V) Output Low Voltage
(1)
I
OL
= +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3.3V) Output High Voltage
(1)
I
OH
= -4mA, V
DDQ
= Min. 2.4
___
V
V
OL
(2.5V) Output Low Voltage
(1)
I
OL
= +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2.5V) Output High Voltage
(1)
I
OH
= -2mA, V
DDQ
= Min. 2.0
___
V
5666 tbl 08
NOTES:
1. V
DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.

70T3599S200BC

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 128Kx36 STD-PWR 2.5V DUAL PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
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