Enhanced Product ADM3095E-EP
Rev. 0 | Page 7 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
V
CC
2
V
IO
3
TxD
4
GND
16
GND
15
B
14
GND
DE
5
13
GND
RE
6
12
A
RxD
7
11
GND
GND
8
10
GND
9
ADM3095E-EP
(Not to Scale)
TOP VIEW
15680-002
Figure 6. ADM3095E-EP Pin Configuration
Table 5. ADM3095E-EP Pin Descriptions
Pin No. Mnemonic Description
1, 8 to 10,
12, 13, 15, 16
GND Ground.
2 V
CC
3.0 V to 5.5 V Power Supply. It is recommended that a 0.1 µF decoupling capacitor is added between Pin V
CC
and Pin GND.
3 V
IO
1.62 V to 5.5 V V
IO
Logic Supply. It is recommended that a 0.1 µF decoupling capacitor is added between
Pin V
IO
and Pin GND.
4 TxD Transmit Data Input. Data transmitted by the driver is applied to this input.
5 DE Driver Output Enable. A high level on this pin enables the A and B driver differential outputs. A low level
places them into a high impedance state.
6
RE
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving the
input high disables the receiver.
7 RxD Receiver Output Data. This output is high when (A − B) > –30 mV and low when (A − B) < −200 mV.
11 A Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V
CC
is powered down, Pin A
is put into a high impedance state to avoid overloading the bus.
14 B Inverting Driver Output/Receiver Input. When the driver is disabled, or when V
CC
is powered down, Pin B is
put into a high impedance state to avoid overloading the bus.