PCA9552_5 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 05 — 9 March 2006 10 of 28
Philips Semiconductors
PCA9552
16-bit I
2
C-bus LED driver with programmable blink rates
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 7).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8.)
7.2 System configuration
A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. The
device that controls the message is the ‘master' and the devices which are controlled by
the master are the ‘slaves' (see Figure 9).
Fig 7. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 8. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
PCA9552_5 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 05 — 9 March 2006 11 of 28
Philips Semiconductors
PCA9552
16-bit I
2
C-bus LED driver with programmable blink rates
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
Fig 10. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCA9552_5 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 05 — 9 March 2006 12 of 28
Philips Semiconductors
PCA9552
16-bit I
2
C-bus LED driver with programmable blink rates
7.4 Bus transactions
Fig 11. Write to register
0 AS
slave address
START condition R/W acknowledge
from slave
002aac185
0 0 AI B3 B2 B1 B00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
write to register
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to register
1 0 0 A2 A1 A01
Fig 12. Read from register
1 0 0 A2 A1 A0 0 AS1
START condition R/W
acknowledge
from slave
002aac186
A
acknowledge
from slave
SDA
A P
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 0 0 A2 A1 A0 1 A1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
command byte
0 0 AI B3 B2 B10B0
Auto-Increment
register address
if AI = 1
Remark: This figure assumes the command byte has previously been programmed with 00h.
Fig 13. Read Input Port register
1 0 0 A2 A1 A0 1 AS1
START condition R/W acknowledge
from slave
002aac187
A
acknowledge
from master
SDA NA
read from
port
data into
port
P
t
h(D)
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
t
su(D)

PCA9552BS,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 16-BIT I2C FM OD LED BLK RST
Lifecycle:
New from this manufacturer.
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