19
FN6315.1
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part in these equations, and a typical value was chosen for
example purposes. For a robust design, a margin of 30%
should be included to cover supply current and capacitance
tolerances over the results of the calculations. Even more
margin should be included if periods of very warm
temperature operation are expected.
Example 1. Calculating Backup Time Given
Voltages and Capacitor Value
In Figure 20, use C
BAT
= 0.47F and V
CC
= 5.0V. With V
CC
=
5.0V, the voltage at V
BAT
will approach 4.7V as the diode
turns off completely. The ISL1220 is specified to operate
down to V
BAT
= 1.8V. The capacitance charge/discharge
equation is used to estimate the total backup time:
Rearranging gives:
C
BAT
is the backup capacitance and dV is the change in
voltage from fully charged to loss of operation. Note that
I
TOT
is the total of the supply current of the ISL1220 (I
BAT
)
plus the leakage current of the capacitor and the diode, I
LKG
.
In these calculations, I
LKG
is assumed to be extremely small
and will be ignored. If an application requires extended
operation at temperatures over 50°C, these leakages will
increase and hence reduce backup time.
Note that I
BAT
changes with V
BAT
almost linearly (see
Typical Performance Curves). This allows us to make an
approximation of I
BAT
, using a value midway between the
two endpoints. The typical linear equation for I
BAT
vs V
BAT
is:
Using this equation to solve for the average current given 2
voltage points gives:
Combining with Equation 2 gives the equation for backup
time:
where
C
BAT
= 0.47F
V
BAT2
= 4.7V
V
BAT1
= 1.8V
I
LKG
= 0 (assumed minimal)
Solving equation 4 for this example, I
BATAVG
= 4.387E-7 A
T
BACKUP
= 0.47 * (2.9) / 4.38E-7 = 3.107E6 sec
Since there are 86,400 seconds in a day, this corresponds to
35.96 days. If the 30% tolerance is included for capacitor
and supply current tolerances, then worst case backup time
would be:
C
BAT
= 0.70 * 35.96 = 25.2 days
Example 2. Calculating a Capacitor Value for a
Given Backup Time
Referring to Figure 20 again, the capacitor value needs to be
calculated to give 2 months (60 days) of backup time, given
V
CC
= 5.0V. As in Example 1, the V
BAT
voltage will vary from
4.7V down to 1.8V. We will need to rearrange Equation 2 to
solve for capacitance:
Using the terms described above, this equation becomes:
where:
T
BACKUP
= 60 days * 86,400 sec/day = 5.18 E6 sec
I
BATAVG
= 4.387 E-7 A (same as Example 1)
I
LKG
= 0 (assumed)
V
BAT2
= 4.7V
V
BAT1
= 1.8V
Solving gives:
C
BAT
= 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F
If the 30% tolerance is included for tolerances, then worst
case cap value would be:
C
BAT
= 1.3 *.784 = 1.02F
FIGURE 20. SUPERCAPACITOR CHARGING CIRCUIT
2.7V to 5.5V
V
CC
V
BAT
GND
1N4148
C
BAT
I = C
BAT
* dV/dT
(EQ. 1)
dT = C
BAT
* dV/I
TOT
to solve for backup time.
(EQ. 2)
I
BAT
= 1.031E-7*(V
BAT
) + 1.036E-7 Amps
(EQ. 3)
I
BATAVG
= 5.155E-8*(V
BAT2
+ V
BAT1
) + 1.036E-7 Amps
(EQ. 4)
T
BACKUP
= C
BAT
* (V
BAT2
- V
BAT1
) / (I
BATAVG
+ I
LKG
)
(EQ. 5)
seconds
C
BAT
= dT*I/dV
(EQ. 6)
C
BAT
= T
BACKUP
* (I
BATAVG
+ I
LKG
)/(V
BAT2
– V
BAT1
)
(EQ. 7)
ISL1220
20
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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FN6315.1
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About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
August 7, 2015 FN6315.1 Added Revision History beginning with Rev 1.
Added About Intersil Verbiage.
Updated Ordering Information Table.
Updated M10.118 to new POD template. Added land pattern.
ISL1220
21
FN6315.1
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ISL1220
Package Outline Drawing
M10.118
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 4/12
DETAIL "X"
SIDE VIEW 2
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
PIN# 1 ID
0.18 - 0.27
DETAIL "X"
0.10 ± 0.05
(4.40)
(3.00)
(5.80)
H
C
1.10 MAX
0.09 - 0.20
3°±3°
GAUGE
PLANE
0.25
0.95 REF
0.55 ± 0.15
B
0.08 C A-B
D
3.0±0.05
12
10
0.85±010
SEATING PLANE
A
0.50 BSC
3.0±0.05
4.9±0.15
(0.29)
(1.40)
(0.50)
D
5
5
SIDE VIEW 1
Dimensioning and tolerancing conform to JEDEC MO-187-BA
Plastic interlead protrusions of 0.15mm max per side are not
Dimensions in ( ) are for reference only.
Dimensions are measured at Datum Plane "H".
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions are in millimeters.
3.
4.
5.
6.
NOTES:
1.
2.
and AMSEY14.5m-1994.
included.
included.
0.10 C
M

ISL1220IUZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLKRTC IN
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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