4
FN6315.1
August 7, 2015
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V
IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x
V
DD
V
DD
+
0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x
V
DD
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 3mA
00.4V
Cpin SDA and SCL Pin Capacitance T
A
= 25°C, f = 1MHz, V
DD
= 5V, V
IN
=0V,
V
OUT
= 0V
10 pF
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50 ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of V
DD
, until
SDA exits the 30% to 70% of V
DD
window.
900 ns
t
BUF
Time the Bus Must be Free before
the Start of a New Transmission
SDA crossing 70% of V
DD
during a STOP
condition, to SDA crossing 70% of V
DD
during the following START condition.
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing. 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing. 600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30% of V
DD
to SCL falling edge crossing 70% of V
DD
.
600 ns
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD
100 ns
t
HD:DAT
Input Data Hold Time From SCL falling edge crossing 30% of V
DD
to SDA entering the 30% to 70% of V
DD
window.
0 900 ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge crossing 70% of V
DD
,
to SDA rising edge crossing 30% of V
DD
.
600 ns
t
HD:STO
STOP condItion Hold Time From SDA rising edge to SCL falling edge.
Both crossing 70% of V
DD
.
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
0ns
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20 +
0.1 x Cb
300 ns 6
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20 +
0.1 x Cb
300 ns 6
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 6
Rpu SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k.
For Cb = 40pF, max is about 15~20k
1k 6
NOTES:
2. IRQ
and F
OUT
Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if V
DD
> V
BAT
, otherwise the device will be unable to communicate using I
2
C.
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 5) MAX UNITS NOTES
ISL1220