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SL2305ZI-1HT

P1-P3P4-P6P7-P9P10-P12
Rev 0.1 9/13 Page 1 of 11
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
SL2305
Not Recommended for New Designs
Key Features
10 to 140 MHz operating frequency range
Low output clock jitter:
- 140 ps-max c-c-j at 66 MHz
Low output-to-output skew: 150 ps-max
Low product-to-product skew: 400 ps-max
3.3 V power supply range
Low power dissipation:
- 14 mA-max at 66MHz
- 26 mA-max at 133 MHz
One input drives 5 outputs organized as 4+1
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 8-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL2305 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to five (5) clock
outputs from one (1) reference input clock for high speed
clock distribution applications. The product has an on-chip
PLL which locks to the input clock at CLKIN and receives its
feedback internally from the CLKOUT pin.
The SL2305 is available with two (2) drive strength versions.
The -1 is the standard-drive version and -1H is the high-
drive version.
The SL2305 high-drive version operates up to 140MHz and
the standard drive version -1 operates up to 100.
The SL2305 enter into Power-Down (PD) mode if the input
at CLKIN is DC (0 to VDD). In this power-down state all five
(5) outputs are tri-stated and the PLL is turned off leading to
less than 12μA-max of power supply current draw.
Benefits
Up to five (5) distribution of input clock
Standard and High-Drive levels to control impedance
level, frequency range and EMI
Low jitter and skew
Low power dissipation
Low cost
Block Diagram
PLL
VDD
GND
CLKIN
CLKOUT
CLK1
CLK2
CLK3
CLK4
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Not Recommended
for New Designs
Rev 0.1 9/13 Page 2 of 11
SL2305
8-Pin SOIC or TSSOP
Pin Description
Pin Configuration
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
Reference Frequency Clock Input. Weak pull-down (250kΩ).
2
CLK2
Output
Buffered Clock Output Weak pull-down (250kΩ).
3
CLK1
Output
Buffered Clock Output. Weak pull-down (250kΩ).
4
GND
Power
Power Ground.
5
CLK3
Output
Buffered Clock Output. Weak pull-down (250kΩ).
6
VDD
Power
3.3V Power Supply.
7
CLK4
Output
Buffered Clock Output. Weak pull-down (250kΩ).
8
CLKOUT
Output
Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull-
down (250kΩ).
Not Recommended
for New Designs
Rev 0.1 9/13 Page 3 of 11
SL2305
General Description
The SL2305 is a low skew, low jitter Zero Delay Buffer with
very low operating power supply current (IDD).
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces five (5)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
In addition to CLKOUT that is used for internal PLL
feedback, there is a single bank with four (4) outputs,
bringing the number of total available output clocks to five
(5).
Input and output Frequency Range
The input and output frequency range is the same. But, the
frequency range depends on the drive levels and load
capacitance (CL) as given in the below Table 1.
Drive
CL(pF)
Min(MHz)
Max(MHz)
HIGH (-1H)
15
10
140
HIGH (-1H)
30
10
100
STD (-1)
15
10
100
STD (-1)
30
10
66
Table 1. Input/Output Frequency Range
If the input clock frequency is DC (0 to VDD), this is
detected by an input detection circuitry and all five (5) clock
outputs are forced to Hi-Z. The PLL is shutdown to save
power. In this shutdown state, the product draws less than
12μA-max supply current.
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL2305 is designed to pass the modulated
Spread Spectrum Clock (SSC) signal from its CLKIN
(reference) input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency.
High and Low-Drive Product Options
The SL2305 is offered with High-Drive “-1H” and Standard-
Drive “-1” options. These drive options enable the users to
control load levels, frequency range and EMI control. Refer
to the AC electrical tables for the details.
Skew and Zero Delay
All outputs should drive the similar load to achieve output-
to-output and input-to-output skew specifications given in
the AC electrical tables.
However, Zero delay between input and outputs can be
adjusted by changing the loading of CLKOUT relative to the
other clock outputs since CLKOUT is the feedback to the
PLL.
Power Supply Range (VDD)
The SL2305 is designed to operate from 3.0V (Min) to 3.6V
(Max), complying with VDD=3.3V+/-10% requirement.
An internal on-chip voltage regulator is used to supply PLL
constant power supply of 1.8V, leading to a consistent and
stable PLL electrical performance in terms of skew, jitter
and power dissipation.
Temperature Range and Packages
The SL2305 is offered with commercial temperature range
of 0 to +70°C (C-Grade) and industrial temperature range of
-40 to +85°C (I-Grade).
The SL2305 is available in 8-pin SOIC (150-mil) and 8-pin
TSSOP (173-mil) packages.
SL23EP05
Refer to SL23EP05 for extended frequency operation from
10 to 220MHz and 2.5V to 3.3V power supply operation
range.
Absolute Maximum Ratings
Description
Condition
Min
Max
Unit
Supply voltage, VDD
– 0.5
4.6
V
All Inputs and Outputs
– 0.5
VDD+0.5
V
Ambient Operating Temperature
In operation, C-Grade
0
70
°C
Ambient Operating Temperature
In operation, I-Grade
– 40
85
°C
Storage Temperature
No power is applied
– 65
150
°C
Junction Temperature
In operation, power is applied
–
125
°C
Not Recommended
for New Designs
P1-P3P4-P6P7-P9P10-P12

SL2305ZI-1HT

Mfr. #:
Buy SL2305ZI-1HT
Manufacturer:
Silicon Labs
Description:
Clock Buffer 10 to 140MHz, 5 Outputs Zero Delay Buffer (ZDB), 3.3V High Drive
Lifecycle:
New from this manufacturer.
Delivery:
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