P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 11 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P1.5/RST 47 5 43 I P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or maybe a
reset input/output if selected via UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above
12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until V
DD
has reached its
specified level. When system power is removed V
DD
will
fall below the minimum specified operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
P1.6 46 4 42 I/O P1.6 — Port 1 bit 6.
P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit 7.
I AD04 — ADC0 channel 4 analog input.
P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable
output type. During reset Port 2 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 2 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to
Section 7.13.1 “Port configurations”
and
Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit 0.
I AD07 — ADC0 channel 7 analog input.
P2.1/AD06 41 44 38 I/O P2.1 — Port 2 bit 1.
I AD06 — ADC0 channel 6 analog input.
P2.2/MOSI 30 34 28 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as
master, this pin is output; when configured as slave, this pin
is input.
P2.3/MISO 29 33 27 I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when
configured as slave, this pin is output.
P2.4/
SS 28 32 26 I/O P2.4 — Port 2 bit 4.
I/O
SS — SPI Slave select.
Table 3. Pin description
…continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44