P89LPC954FBD48,151 Datasheet P89LPC954FBD48,151, P89LPC952FBD,157, P89LPC954FBD44,151 | P46-P48

Product data sheet Rev. 04 — 24 July 2008 46 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.26.9 Power-on reset code execution

The P89LPC952/954 contains two special ﬂash elements: the Boot Vector and the Boot

Status bit. Following reset, the P89LPC952/954 examines the contents of the Boot Status

bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which

is the normal start address of the user’s application code. When the Boot Status bit is set

to a value other than zero, the contents of the Boot Vector are used as the high byte of the

execution address and the low byte is set to 00H.

Table 9 shows the factory default Boot Vector setting for these devices. A factory-provided

bootloader is pre-programmed into the address space indicated and uses the indicated

bootloader entry point to perform ISP functions. This code can be erased by the user.

Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be

used to erase the ﬁrst eight 64-byte pages located in this sector. A custom

bootloader can be written with the Boot Vector set to the custom bootloader, if desired.

7.26.10 Hardware activation of the bootloader

The bootloader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC952/954

User’s Manual

for speciﬁc information).

This has the same effect as having a non-zero status byte. This allows an application to

be built that will normally execute user code but can be manually forced into ISP

operation. If the factory default setting for the boot vector (1FH/3FH) is changed, it will no

longer point to the factory pre-programmed ISP bootloader code. After programming the

ﬂash, the status byte should be programmed to zero in order to allow execution of the

user’s application code beginning at address 0000H.

7.27 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC952/954 must be deﬁned at power-up and

therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC952/954

User’s Manual

for additional details.

7.28 User sector security bytes

There are eight/sixteen User Sector Security Bytes on the P89LPC952/954. Each byte

corresponds to one sector. Please see the P89LPC952/954

User’s Manual

for additional

details.

Table 9. Default boot vector values and ISP entry points

Device Default

boot vector

Default

bootloader

entry point

Default bootloader

code range

1 kB sector

range

P89LPC952 1FH 1F00H 1E00H to 1FFFH 1C00H to 1FFFH

P89LPC954 3FH 3F00H 3E00H to 3FFFH 3C00H to 3FFFH

Product data sheet Rev. 04 — 24 July 2008 47 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

8. ADC

8.1 General description

The P89LPC952/954 has a 10-bit, 8-channel multiplexed successive approximation ADC

module. A block diagram of the ADC is shown in Figure 17. The ADC consists of an

8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one

of two comparator inputs. The control logic in combination with the SAR drives a DAC

which provides the other input to the comparator. The output of the comparator is fed to

the SAR.

8.2 Features

n 10-bit, 8-channel multiplexed input, successive approximation ADC.

n Eight result register pairs.

n Six operating modes:

u Fixed channel, single conversion mode.

u Fixed channel, continuous conversion mode.

u Auto scan, single conversion mode.

u Auto scan, continuous conversion mode.

u Dual channel, continuous conversion mode.

u Single step mode.

n Three conversion start modes:

u Timer triggered start.

u Start immediately.

u Edge triggered.

n 10-bit conversion time of 4 µs at an A/D clock of 9 MHz.

n Interrupt or polled operation.

n High and low boundary limits interrupt; selectable in or out-of-range.

n Clock divider.

n Power-down mode.

8.3 Block diagram

Fig 17. ADC block diagram

–

comp

DAC0

SAR

INPUT

MUX

CONTROL

LOGIC

CCLK

002aab103

Product data sheet Rev. 04 — 24 July 2008 48 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register pair which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after the conversion

completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the eight result register pairs. The user may

select whether an interrupt can be generated after every four or every eight conversions.

Additional conversion results will again cycle through the result register pairs, overwriting

the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

whether an interrupt, if enabled, will be generated after either the ﬁrst four conversions

have occurred or all selected channels have been converted. If the user selects to

generate an interrupt after the four input channels have been converted, a second

interrupt will be generated after the remaining input channels have been converted. If only

a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register pair

which corresponds to the selected input channel. The user may select whether an

interrupt, if enabled, will be generated after either the ﬁrst four conversions have occurred

or all selected channels have been converted. If the user selects to generate an interrupt

after the four input channels have been converted, a second interrupt will be generated

after the remaining input channels have been converted. After all selected channels have

been converted, the process will repeat starting with the ﬁrst selected channel. Additional

conversion results will again cycle through the eight result register pairs, overwriting the

previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the

second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The ﬁrst

channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The

second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L,

etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user

selectable).

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