ADuM230D/ADuM230E/ADuM231D/ADuM231E Data Sheet
Rev. A | Page 18 of 21
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM230D/ADuM230E/ADuM231D/ADuM231E digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
the input and output supply pins (see Figure 18). Bypass capaci-
tors are most conveniently connected between Pin 1 and Pin 2
for V
DD1
and between Pin 15 and Pin 16 for V
DD2
. The recom-
mended bypass capacitor value is between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin must not exceed 10 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 must
also be considered, unless the ground pair on each package side
is connected close to the package.
Figure 18. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time
required for a logic signal to propagate through a component.
The propagation delay to a Logic 0 output may differ from the
propagation delay to a Logic 1 output.
Figure 19. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM230D/
ADuM230E/ADuM231D/ADuM231E component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM230D/ADuM230E/
ADuM231D/ADuM231E components operating under the
same conditions.
JITTER MEASUREMENT
Figure 20 shows the eye diagram for the ADuM230D/ADuM230E/
ADuM231D/ADuM231E. The measurement was taken using an
Agilent 81110A pulse pattern generator at 150 Mbps with
pseudorandom bit sequences (PRBS), 2(n − 1), n = 14, for 5 V
supplies. Jitter was measured with the Tektronix Model 5104B
oscilloscope, 1 GHz, 10 GSPS with the DPOJET jitter and eye
diagram analysis tools. The result shows a typical measurement
on the ADuM230D/ADuM230E/ADuM231D/ADuM231E with
630 ps p-p jitter.
Figure 20. Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components, which allows
the components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and, therefore, can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
V
DD1
GND
1
V
IA
V
IB
V
IC
/V
OC
NIC
DISABLE
1
/V
E1
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
/V
OC
NIC
DISABLE
2
/V
E2
GND
2
13577-010
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
13577-011
105
0
1
2
3
4
VOL
AGE (V)
5
0
TIME (ns)
–5–10
13577-012
