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LTC1274CSW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
10
LTC1274/LTC1277
TI I G DIAGRA S
W
W
U
CS to RD Setup Timing
CS to CONVST Setup Timing
t
1
CS
RD
LTC1274/77 • TD01
t
2
CS
CONVST
LTC1274/77 • TD02
NAP to CONVST Wake-Up Timing (LTC1277)
SLEEP to REFRDY Wake-Up Timing
t
3
NAP
CONVST
LTC1274/77 • TD03
t
14
SLEEP
REFRDY
LTC1274/77 • TD04
APPLICATIONS INFORMATION
WUU
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CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation
algorithm and an internal sample-and-hold circuit to con-
vert an analog signal to a 12-bit parallel output. The ADCs
are complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC out-
put is sequenced by the SAR from the most significant bit
(MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
(LTC1274) or A
IN
+
(LTC1277) input con-
nects to the sample-and-hold capacitor during the acquire
phase, and the comparator offset is nulled by the feedback
switch. In this acquire phase, a minimum delay of 2µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
comparator feedback switch opens, putting the comparator
into the compare mode. The input switch connects C
SAMPLE
to ground (LTC1274) or A
IN
–
(LTC1277), injecting the
analog input charge onto the summing junction. This input
charge is successively compared with the binary-weighted
charges supplied by the capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the DAC output balances the A
IN
(LTC1274) or
A
IN
+
– A
IN
–
(LTC1277) input charge. The SAR contents (a 12-
bit data word) which represent the A
IN
(LTC1274) or
A
IN
+
– A
IN
–
(LTC1277) are loaded into the 12-bit output latches.
V
DAC
1274 • F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
12-BIT
LATCH
COMPAR-
ATOR
SAMPLE
SI
A
IN
Figure 1. LTC1274 A
IN
Input
DYNAMIC PERFORMANCE
The LTC1274/LTC1277 have excellent high speed sam-
pling capability. FFT (Fast Fourier Transform) test tech-
niques are used to test the ADCs’ frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
11
LTC1274/LTC1277
APPLICATIONS INFORMATION
WUU
U
using an FFT algorithm, the ADCs’ spectral content can be
examined for frequencies outside the fundamental. Figures
2a and 2b show typical LTC1274 FFT plots.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies above DC and below half the sam-
pling frequency. Figure 2a shows a typical spectral content
with a 100kHz sampling rate and a 48.85kHz input. The
dynamic performance is excellent for input frequencies well
beyond Nyquist as shown in Figure 2b and Figure 3.
INPUT FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10 20 30 40
LTC1274/77 • F02a
50
f
SAMPLE
= 100kHz
f
IN
= 48.85kHz
Figure 2a. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 50kHz Input Frequency
INPUT FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10 20 30 40
LTC1274/77 • F02b
50
f
SAMPLE
= 100kHz
f
IN
= 97.68kHz
Figure 2b. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 100kHz Input Frequency
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 100kHz, the LTC1274/LTC1277 maintain very
good ENOBs over 300kHz. Refer to Figure 3.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling
frequency. THD is expressed as:
THD = 20log
√V
2
2
+ V
3
2
+ V
4
2
... + V
N
2
V
1
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics. THD versus input fre-
INPUT FREQUENCY (Hz)
10k
EFFECTIVE NUMBER OF BITS (ENOBs)
12
11
10
9
8
7
6
5
4
3
2
1
0
S/(N + D)(dB)
74
68
62
56
50
100k 1M 2M
LTC1274/77 • F03
f
SAMPLE
= 100kHz
NYQUIST
FREQUENCY
Figure 3. ENOBs and S/(N + D) vs Input Frequency
12
LTC1274/LTC1277
APPLICATIONS INFORMATION
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Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1274/LTC1277 have been designed to optimize input
bandwidth, allowing ADCs to undersample input signals
with frequencies above the converter’s Nyquist frequency.
The noise floor stays very low at high frequencies;
S/(N + D) becomes dominated by distortion at frequencies
far beyond Nyquist.
Driving the Analog Input
The analog input of the LTC1274/LTC1277 is easy to
drive. It draws only one small current spike while charg-
ing the sample-and-hold capacitor at the end of conver-
sion. During conversion the analog input draws only a
small leakage current. The only requirement is that the
amplifier driving the analog input must settle after the
small current spike before the next conversion starts.
Any op amp that settles in 2µs to small current transients
will allow maximum speed operation. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions. Suitable devices capable of
driving the ADC A
IN
input include the LT
®
1006, LT1007,
LT1220, LT1223 and LT1224 op amps.
quency is shown in Figure 4. The ADCs have good distor-
tion performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can pro-
duce intermodulation distortion (IMD) in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of the
2nd order IMD products can be expressed by the following
formula:
IMD (fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 97kHz input.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
Figure 4. Distortion vs Input Frequency
Figure 5. Intermodulation Distortion
FREQUENCY (Hz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
10k 20k 30k 40k
LTC1274/77 • F05
50k
2fb – fa
fb
fa
fb – fa
2fb
2fa – fb
2fa
3fb
2fb + fa
2fa + fb
fa + fb
3fa
f
SAMPLE
= 100kHz
fa = 96.948kHz
fb = 97.681kHz
THD
INPUT FREQUENCY (Hz)
10k
DISTORTION (dB)
0
–20
–40
–60
–80
–100
–120
100k 1M 2M
LTC1274/77 • F04
3RD HARMONIC
2ND HARMONIC
f
SAMPLE
= 100kHz
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LTC1274CSW#PBF

Mfr. #:
Buy LTC1274CSW#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 10mW, 100ksps ADCs w/ 1 A SD
Lifecycle:
New from this manufacturer.
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